Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC86102L, MOSFET

June 2014

FDMC86102L Rev.C4

www.fairchildsemi.com

FDMC86102L N-Channel Shielded Gate PowerTrench

MOSFET

FDMC86102L

N-Channel Shielded Gate PowerTrench

MOSFET

100 V, 18 A, 23 mΩ

Features

 Shielded Gate MOSFET Technology

 Max r

DS(on)

= 23 mΩ at V

= 10 V, I

= 7 A

 Max r

DS(on)

= 34 mΩ at V

= 4.5 V, I

= 5.5 A

 Low Profile - 1 mm max in Power 33

 RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor‘s advanced PowerTrench

process that

incorporates Shielded Gate technology. This process has been

optimized for the on-state resistance and yet maintain superior

switching performance.

Application

 DC - DC Conversion

Bottom

Top

Pin 1

MLP 3.3x3.3

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 100 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 18

A -Continuous T

= 25 °C (Note 1a) 7

-Pulsed 30

Single Pulse Avalanche Energy (Note 3) 63 mJ

Power Dissipation T

= 25 °C 41

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 3

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC86102L FDMC86102L Power 33 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMC86102L N-Channel Shielded Gate PowerTrench® MOSFET 100 V, 18 A, 23 mΩ Features General Description Shielded Gate MOSFET Technology This N-Channel MOSFET is produced using Fairchild Semiconductor‘s advanced PowerTrench® process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. Max rDS(on) = 23 mΩ at VGS = 10 V, ID = 7 A Max rDS(on) = 34 mΩ at VGS = 4.5 V, ID = 5.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 3 V 100 V 71 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source
PAGE 3
5 VGS = 10 V 25 VGS = 4.5 V VGS = 4 V 20 VGS = 3.5 V 15 VGS = 3 V 10 5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 30 4 VGS = 3 V 3 VGS = 3.5 V 2 1 0 5 10 15 20 25 30 ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance vs. Drain Current and Gate Voltage 120 ID = 7 A VGS = 10 V 1.8 rDS(on), DRAIN TO 1.6 1.4 1.2 1.
PAGE 4
2000 1000 ID = 7 A Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 25 V 6 VDD = 50 V 4 VDD = 75 V Coss 100 10 Crss 2 f = 1 MHz VGS = 0 V 0 0 4 8 12 1 0.1 16 1 Figure 7. Gate Charge Characteristics 30 10 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 100 Figure 8. Capacitance vs. Drain to Source Voltage 30 TJ = 25 oC TJ = 100 oC TJ = 125 oC 25 20 VGS = 10 V 15 Limited by package VGS = 4.5 V 10 5 o RθJC = 3 C/W 1 0.01 0.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2010 Fairchild Semiconductor Corporation FDMC86102L Rev.C4 5 www.fairchildsemi.
PAGE 6
FDMC86102L N-Channel Shielded Gate PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.