Datasheet

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June 2014

FDMC86102LZ N-Channel Shielded Gate PowerTrench

MOSFET

FDMC86102LZ Rev. C4

FDMC86102LZ

N-Channel Shielded Gate PowerTrench

MOSFET

100 V, 22 A, 24 mΩ

Features

 Shielded Gate MOSFET Technology

 Max r

DS(on)

= 24 mΩ at V

= 10 V, I

= 6.5 A

 Max r

DS(on)

= 35 mΩ at V

= 4.5 V, I

= 5.5 A

 HBM ESD protection level > 6 KV typical (Note 4)

 100% UIL Tested

 RoHS Compliant

General Description

This N-Channel logic Level MOSFETs are produced using

Fairchild Semiconductor‘s advanced PowerTrench

process

that incorporates Shielded Gate technology. This process has

been optimized

for the on-state resistance and yet maintain

superior switching performance. G-S zener has been added to

enhance ESD voltage level.

Application

 DC - DC Switching

Bottom

Top

Pin 1

MLP 3.3x3.3

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 100 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 22

A -Continuous T

= 25 °C (Note 1a) 7

-Pulsed 30

Single Pulse Avalanche Energy (Note 3) 84 mJ

Power Dissipation T

= 25 °C 41

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 3

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC86102Z FDMC86102LZ Power 33 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMC86102LZ N-Channel Shielded Gate PowerTrench® MOSFET 100 V, 22 A, 24 mΩ Features General Description Shielded Gate MOSFET Technology This N-Channel logic Level MOSFETs are produced using Fairchild Semiconductor‘s advanced PowerTrench® process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. G-S zener has been added to enhance ESD voltage level. Max rDS(on) = 24 mΩ at VGS = 10 V, ID = 6.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±10 μA 2.
PAGE 3
8 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 30 VGS = 10 V ID, DRAIN CURRENT (A) 25 VGS = 4.5 V 20 VGS = 3.5 V VGS = 3 V 15 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 2.5 V 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 7 VGS = 2.5 V 6 5 VGS = 3 V 4 3 VGS = 3.5 V 2 1 0 5 10 15 20 25 30 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics Figure 2. Normalized On-Resistance vs. Drain Current and Gate Voltage 2.0 1.8 rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.
PAGE 4
5000 VGS, GATE TO SOURCE VOLTAGE (V) 10 ID = 6.5 A Ciss VDD = 25 V 1000 CAPACITANCE (pF) 8 VDD = 50 V 6 VDD = 75 V 4 Coss 100 Crss 10 2 f = 1 MHz VGS = 0 V 0 0 4 8 12 1 0.1 16 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain to Source Voltage 30 50 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 3.
PAGE 5
2000 P(PK), PEAK TRANSIENT POWER (W) 1000 100 10 SINGLE PULSE o RθJA = 125 C/W o TA = 25 C 1 0.5 -4 10 -3 -2 10 -1 10 10 1 100 10 1000 t, PULSE WIDTH (sec) Figure 13. Single Pulse Maximum Power Dissipation 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 0.
PAGE 6
FDMC86102LZ N-Channel Shielded Gate PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.