Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC86160, MOSFET

January 2013

FDMC86160 Rev. C1

www.fairchildsemi.com

FDMC86160 N-Channel Power Trench

MOSFET

FDMC86160

N-Channel Power Trench

MOSFET

100 V, 43 A, 14 mΩ

Features

 Max r

DS(on)

= 14 mΩ at V

= 10 V, I

= 9 A

 Max r

DS(on)

= 23 mΩ at V

= 6 V, I

= 7 A

 High performance technology for extremely low r

DS(on)

 Termination is Lead-free and RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced PowerTrench

® process that has

been especially tailored to minimize the on-state resistance. This

device is well suited for applications where ulta low R

DS （on）

required in small spaces such as High performance VRM, POL

and orring functions.

Applications

 Bridge Topologies

 Synchronous Rectifier

BottomTop

Pin 1

Power 33

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 100 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 43

A -Continuous T

= 25 °C (Note 1a) 9

-Pulsed 50

Single Pulse Avalanche Energy (Note 3) 181 mJ

Power Dissipation T

= 25 °C 54

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case (Note 1) 2.3

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC86160 FDMC86160 Power33 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMC86160 N-Channel Power Trench® MOSFET 100 V, 43 A, 14 mΩ Features General Description Max rDS(on) = 14 mΩ at VGS = 10 V, ID = 9 A This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that has been especially tailored to minimize the on-state resistance. This device is well suited for applications where ulta low RDS （on） is required in small spaces such as High performance VRM, POL and orring functions.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4 V 100 V 73 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source
PAGE 3
5 VGS = 10 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 50 VGS = 7 V 40 VGS = 6 V VGS = 5.5 V 30 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 20 VGS = 5 V 10 VGS = 4.5 V 0 0 1 2 3 4 VGS = 4.5 V VGS = 5 V 4 VGS = 5.5 V 3 VGS = 6 V 2 VGS = 7 V 1 0 5 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 60 rDS(on), DRAIN TO 1.8 1.6 1.4 1.2 1.0 0.8 0.6 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID = 9 A VGS = 10 V 0.
PAGE 4
10000 ID = 9 A VDD = 50 V Ciss 8 VDD = 25 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 75 V 6 4 1000 Coss 100 10 2 0 0 4 8 12 1 0.1 16 1 Figure 7. Gate Charge Characteristics 100 Figure 8. Capacitance vs Drain to Source Voltage 100 ID, DRAIN CURRENT (A) 50 TJ = 25 oC TJ = 100 oC 10 TJ = 125 oC 40 VGS = 10 V 30 VGS = 6 V 20 10 o RθJC = 2.3 C/W 1 0.001 0.01 0.1 1 10 0 25 100 50 tAV, TIME IN AVALANCHE (ms) 125 150 Figure 10.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDMC86160 Rev. C1 5 www.fairchildsemi.
PAGE 6
FDMC86160 N-Channel Power Trench® MOSFET Dimensional Outline and Pad Layout ©2013 Fairchild Semiconductor Corporation FDMC86160 Rev. C1 6 www.fairchildsemi.
PAGE 7
tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.