Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMC86320, MOSFET

June 2014

FDMC86320 Rev.C2

www.fairchildsemi.com

FDMC86320 N-Channel Power Trench

MOSFET

FDMC86320

N-Channel Power Trench

MOSFET

80 V, 22 A, 11.7 mΩ

Features

 Max r

DS(on)

= 11.7 mΩ at V

= 10 V, I

= 10.7 A

 Max r

DS(on)

= 16 mΩ at V

= 8 V, I

= 8.5 A

 MSL1 robust package design

 100% UIL Tested

 RoHS Compliant

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency and to minimize switch node

ringing of DC/DC converters using either synchronous or

conventional switching PWM controllers.It has been optimized

for low gate charge, low r

DS(on)

, fast switching speed and body

diode reverse recovery performance.

Applications

 Primary DC-DC Switch

 Motor Bridge Switch

 Synchronous Rectifier

Bottom

Top

Pin 1

MLP 3.3x3.3

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 80 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 22

A -Continuous T

= 25 °C (Note 1a) 10.7

-Pulsed 50

Single Pulse Avalanche Energy (Note 3) 60 mJ

Power Dissipation T

= 25 °C 40

Power Dissipation T

= 25 °C (Note 1a) 2.3

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 3.1

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC86320 FDMC86320 Power 33 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMC86320 N-Channel Power Trench® MOSFET 80 V, 22 A, 11.7 mΩ Features General Description Max rDS(on) = 11.7 mΩ at VGS = 10 V, ID = 10.7 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers.It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 64 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4.
PAGE 3
5 VGS = 10 V VGS = 6.5 V VGS = 8 V 40 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 50 VGS = 7 V 30 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 6 V 20 10 VGS = 5.5 V 0 0 1 2 3 4 VGS = 5.5 V VGS = 6.5 V 3 VGS = 7 V 2 VGS = 8 V 1 0 5 0 10 30 40 50 Figure 2. Normalized On-Resistance vs. Drain Current and Gate Voltage 1.8 40 ID = 10.7 A VGS = 10 V rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.
PAGE 4
3000 ID = 10.7 A VDD = 40 V Ciss 1000 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 50 V VDD = 30 V 6 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 10 0 0 5 10 15 20 25 5 0.1 30 Figure 7. Gate Charge Characteristics ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) TJ = 25 oC TJ = 100 oC TJ = 125 oC 0.1 1 40 VGS = 10 V 30 VGS = 8 V 20 10 Limited by Package o RθJC = 3.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W 0.001 0.0005 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMC86320 Rev.C2 5 www.fairchildsemi.
PAGE 6
FDMC86320 N-Channel Power Trench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.