Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDME1024NZT, MOSFET

July 2010

FDME1024NZT Rev.C1

FDME1024NZT Dual N-Channel PowerTrench

MOSFET

www.fairchildsemi.com

FDME1024NZT

Dual N-Channel PowerTrench

MOSFET

20 V, 3.8 A, 66 mΩ

Features

 Max r

DS(on)

= 66 mΩ at V

= 4.5 V, I

= 3.4 A

 Max r

DS(on)

= 86 mΩ at V

= 2.5 V, I

= 2.9 A

 Max r

DS(on)

= 113 mΩ at V

= 1.8 V, I

= 2.5 A

 Max r

DS(on)

= 160 mΩ at V

= 1.5 V, I

= 2.1 A

 Low profile: 0.55 mm maximum in the new package

MicroFET 1.6x1.6 Thin

 Free from halogenated compounds and antimony oxides

 HBM ESD protection level > 1600 V (Note 3)

 RoHS Compliant

General Description

This device is designed specifically as a single package solution

for dual switching requirement in cellular handset and other

ultra-portable applications. It features two independent

N-Channel MOSFETs with low on-state resistance for minimum

conduction losses.

The MicroFET 1.6x1.6 Thin package offers exceptional thermal

performance for it's physical size and is well suited to switching

and linear mode applications.

Applications

 Baseband Switch

 Load Switch

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 20 V

Gate to Source Voltage ±8 V

Drain Current -Continuous T

= 25 °C (Note 1a) 3.8

-Pulsed 6

Power Dissipation for Single Operation T

= 25 °C (Note 1a) 1.4

Power Dissipation for Single Operation T

= 25 °C (Note 1b) 0.6

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient (Single Operation) (Note 1a) 90

°C/W

θJA

Thermal Resistance, Junction to Ambient (Single Operation) (Note 1b) 195

Device Marking Device Package Reel Size Tape Width Quantity

4T FDME1024NZT MicroFET 1.6x1.6 Thin 7 ’’ 8 mm 5000 units

MicroFET 1.6x1.6 Thin

BOTTOM

Pin 1

TOP

Summary of content (7 pages)

PAGE 1
FDME1024NZT Dual N-Channel PowerTrench® MOSFET 20 V, 3.8 A, 66 mΩ Features General Description Max rDS(on) = 66 mΩ at VGS = 4.5 V, ID = 3.4 A This device is designed specifically as a single package solution for dual switching requirement in cellular handset and other ultra-portable applications. It features two independent N-Channel MOSFETs with low on-state resistance for minimum conduction losses. Max rDS(on) = 86 mΩ at VGS = 2.5 V, ID = 2.9 A Max rDS(on) = 113 mΩ at VGS = 1.8 V, ID = 2.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±8 V, VDS = 0 V ±10 μA 1.
PAGE 3
VGS = 4.5 V VGS = 3 V VGS = 2.5 V VGS = 1.8 V 4 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 6 VGS = 1.5 V 2 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.5 1.0 3.0 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 2.5 VGS = 1.5 V 2.0 VGS = 1.8 V 1.5 1.0 VGS = 4.5 V 0.5 1.5 0 2 VDS, DRAIN TO SOURCE VOLTAGE (V) 6 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 300 ID = 3.4 A VGS = 4.5 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.
PAGE 4
500 ID = 3.4 A Ciss CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 4.5 VDD = 8 V 3.0 VDD = 10 V VDD = 12 V 1.5 100 Coss 0.0 0 1 2 10 0.1 3 1 10 20 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 10 -1 10 Ig, GATE LEAKAGE CURRENT (A) 100 μs ID, DRAIN CURRENT (A) Crss f = 1 MHz VGS = 0 V 1 ms 1 10 ms THIS AREA IS LIMITED BY rDS(on) 0.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE 0.01 0.005 -4 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 195 C/W -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve FDME1024NZT Rev.C1 5 www.fairchildsemi.
PAGE 6
FDME1024NZT Dual N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout FDME1024NZT Rev.C1 6 www.fairchildsemi.
PAGE 7
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.