Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDME910PZT, MOSFET

October 2013

FDME910PZT Rev.C2

www.fairchildsemi.com

FDME910PZT P-Channel PowerTrench

MOSFET

FDME910PZT

P-Channel PowerTrench

MOSFET

-20 V, -8 A, 24 mΩ

Features

 Max r

DS(on)

= 24 mΩ at V

= -4.5 V, I

= -8 A

 Max r

DS(on)

= 31 mΩ at V

= -2.5 V, I

= -7 A

 Max r

DS(on)

= 45 mΩ at V

= -1.8 V, I

= -6 A

 Low profile: 0.55 mm maximum in the new package MicroFET

1.6x1.6 Thin

 HBM ESD protection level > 2 kV typical (Note 3)

 Free from halogenated compounds and antimony oxides

 RoHS Compliant

General Description

This device is designed specifically for battery charging or load

switching in cellular handset and other ultraportable applications.

It features a MOSFET with low on-state resistance and zener

diode protection against ESD. The MicroFET 1.6x1.6 Thin

package offers exceptional thermal performance for its physical

size and is well suited to switching and linear mode applications.

MicroFET 1.6x1.6 Thin

TOP

BOTTOM

Pin 1

Bottom Drain Contact

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage -20 V

Gate to Source Voltage ±8 V

-Continuous T

= 25°C (Note 1a) -8

-Pulsed -32

Power Dissipation T

= 25°C (Note 1a) 2.1

Power Dissipation T

= 25°C (Note 1b) 0.7

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 60

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 175

Device Marking Device Package Reel Size Tape Width Quantity

E91 FDME910PZT MicroFET 1.6x1.6 Thin 7 ’’ 8

mm 5000 units

Summary of content (7 pages)

PAGE 1
FDME910PZT P-Channel PowerTrench® MOSFET -20 V, -8 A, 24 mΩ Features General Description This device is designed specifically for battery charging or load switching in cellular handset and other ultraportable applications. It features a MOSFET with low on-state resistance and zener diode protection against ESD. The MicroFET 1.6x1.6 Thin package offers exceptional thermal performance for its physical size and is well suited to switching and linear mode applications. Max rDS(on) = 24 mΩ at VGS = -4.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = -250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = -250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V -1 μA IGSS Gate to Source Leakage Current VGS = ±8 V, VDS = 0 V ±10 μA -1.
PAGE 3
2 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 3 -ID, DRAIN CURRENT (A) VGS = -4.5 V VGS = - 3 V 24 VGS = -2.5 V 16 VGS = -1.8 V 8 VGS = -1.5 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 VGS = -1.5 V VGS = -1.8 V 2 VGS = -2.5 V 1 0 0 8 -VDS, DRAIN TO SOURCE VOLTAGE (V) 24 32 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 120 ID = -8 A VGS = -4.5 V rDS(on), DRAIN TO 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) 1.
PAGE 4
3000 ID = -8 A Ciss VDD = -8 V CAPACITANCE (pF) -VGS, GATE TO SOURCE VOLTAGE (V) 4.5 3.0 VDD = -10 V VDD = -12 V 1.5 1000 Coss Crss f = 1 MHz VGS = 0 V 0.0 0 4 8 12 100 0.1 16 Figure 7. Gate Charge Characteristics -1 20 50 -2 VDS = 0 V 10 -3 -ID, DRAIN CURRENT (A) -Ig, GATE LEAKAGE CURRENT (A) 10 Figure 8. Capacitance vs Drain to Source Voltage 10 10 -4 10 -5 TJ = 125 oC 10 -6 10 -7 10 -8 10 TJ = -9 25 oC 10 1 ms 1 THIS AREA IS LIMITED BY rDS(on) 0.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 0.01 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 175 C/W (Note 1b) 0.001 -3 10 -2 10 -1 0 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDME910PZT Rev.C21 5 www.fairchildsemi.
PAGE 6
FDME910PZT P-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2012 Fairchild Semiconductor Corporation FDME910PZT Rev.C21 6 www.fairchildsemi.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.