Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS3602S, MOSFET

August 2011

FDMS3602S PowerTrench

Power Stage

FDMS3602S Rev.C5

FDMS3602S

PowerTrench

Power Stage

25 V Asymmetric Dual N-Channel MOSFET

Features

Q1: N-Channel

 Max r

DS(on)

= 5.6 mΩ at V

= 10 V, I

= 15 A

 Max r

DS(on)

= 8.1 mΩ at V

= 4.5 V, I

= 14 A

Q2: N-Channel

 Max r

DS(on)

= 2.2 mΩ at V

= 10 V, I

= 26 A

 Max r

DS(on)

= 3.4 mΩ at V

= 4.5 V, I

= 22 A

 Low inductance packaging shortens rise/fall times, resulting in

lower switching losses

 MOSFET integration enables optimum layout for lower circuit

inductance and reduced switch node ringing

 RoHS Compliant

General Description

This device includes two specialized N-Channel MOSFETs in a

dual PQFN package. The switch node has been internally

connected to enable easy placement and routing of synchronous

buck converters. The control MOSFET (Q1) and synchronous

SyncFET (Q2) have been designed to provide optimal power

efficiency.

Applications

 Computing

 Communications

 General Purpose Point of Load

 Notebook VCORE

 Server

PHASE

(S1/D2)

PHASE

Power 56

Top Bottom

Pin 1

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 25 25 V

Gate to Source Voltage (Note 3) ±20 ±20 V

Drain Current -Continuous (Package limited) T

= 25 °C 30 40

-Continuous (Silicon limited) T

= 25 °C 65 135

-Continuous T

= 25 °C 15

-Pulsed 40 100

Single Pulse Avalanche Energy 50

144

Power Dissipation for Single Operation T

= 25°C 2.2

2.5

Power Dissipation for Single Operation T

= 25°C 1.0

1.0

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient 57

°C/WR

θJA

Thermal Resistance, Junction to Ambient 125

120

θJC

Thermal Resistance, Junction to Case 3.5 2

Device Marking Device Package Reel Size Tape Width Quantity

22OA

N7OC

FDMS3602S Power 56 13” 12

mm 3000 units

Summary of content (15 pages)

PAGE 1
FDMS3602S PowerTrench® Power Stage 25 V Asymmetric Dual N-Channel MOSFET Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a Max rDS(on) = 5.6 mΩ at VGS = 10 V, ID = 15 A dual PQFN package. The switch node has been internally Max rDS(on) = 8.1 mΩ at VGS = 4.5 V, ID = 14 A connected to enable easy placement and routing of synchronous buck converters.
PAGE 2
Symbol Parameter Test Conditions Type Min 25 25 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25°C ID = 10 mA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V Q1 Q2 1 500 μA IGSS Gate to Source Leakage Current, Forward VGS = 20 V, VDS = 0 V Q1 Q2 100 100 nA nA 3 3 V V 20 20 mV/°C On C
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 0.8 1.2 1.2 V Q1 Q2 21 28 34 44 ns Q1 Q2 6.6 28 13 44 nC Drain-Source Diode Characteristics VSD Source-Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 15 A VGS = 0 V, IS = 26 A (Note 2) (Note 2) Q1 IF = 15 A, di/dt = 100 A/s Q2 IF = 26 A, di/dt = 300 A/s Notes: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in.
PAGE 4
6 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 40 ID, DRAIN CURRENT (A) VGS = 10 V VGS = 4.5 V 30 VGS = 4 V VGS = 3.5 V 20 10 VGS = 3 V 0 0.0 0.2 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0.4 0.6 0.8 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 5 VGS = 3 V 4 3 VGS = 3.5 V 1 VGS = 10 V 0 1.0 0 10 20 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On Region Characteristics rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.
PAGE 5
2000 VDD = 10 V ID = 15 A Ciss 1000 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 13 V 6 VDD = 16 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 5 10 15 10 0.1 20 1 10 25 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 20 80 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 3.5 C/W 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 60 VGS = 10 V 40 VGS = 4.
PAGE 6
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 SINGLE PULSE 0.01 t2 o RθJA = 125 C/W NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA (Note 1c) 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMS3602S Rev.C5 6 www.fairchildsemi.
PAGE 7
100 8 ID, DRAIN CURRENT (A) 80 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V VGS = 4.5 V VGS = 4 V 60 VGS = 3.5 V 40 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 20 VGS = 3 V 0 0.0 0.2 0.4 0.6 0.8 6 VGS = 3.5 V 4 VGS = 4 V 2 1.0 0 20 40 60 80 100 ID, DRAIN CURRENT (A) Figure 14. On- Region Characteristics Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 rDS(on), DRAIN TO 1.4 1.2 1.0 0.
PAGE 8
10000 ID = 26 A Ciss 8 VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 13 V 4 VDD = 16 V Coss 1000 Crss 2 f = 1 MHz VGS = 0 V 100 0 0 10 20 30 40 50 0.1 50 1 10 25 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 50 150 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o RθJC = 2 C/W TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 120 VGS = 10 V 90 VGS = 4.
PAGE 9
NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 0.01 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 120 C/W 0.001 (Note 1d) 0.0001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMS3602S Rev.C5 9 www.fairchildsemi.
PAGE 10
SyncFET Schottky body diode Characteristics Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3602S.
PAGE 11
1. Switch Node Ringing Suppression Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. Competitors solution Power Stage Device Figure 29.
PAGE 12
FDMS3602S PowerTrench® Power Stage Figure 30. Shows the Power Stage in a buck converter topology 2. Recommended PCB Layout Guidelines As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance.
PAGE 13
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application. 2.
PAGE 14
FDMS3602S PowerTrench® Power Stage Dimensional Outline and Pad Layout ©2011 Fairchild Semiconductor Corporation FDMS3602S Rev.C5 14 www.fairchildsemi.
PAGE 15
tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.