Datasheet

FDMS3668S PowerTrench
®
Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
www.fairchildsemi.com
1
December 2012
FDMS3668S
PowerTrench
®
Power Stage
Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
Max r
DS(on)
= 8 mΩ at V
GS
= 10 V, I
D
= 13 A
Max r
DS(on)
= 11 mΩ at V
GS
= 4.5 V, I
D
= 11 A
Q2: N-Channel
Max r
DS(on)
= 5 mΩ at V
GS
= 10 V, I
D
= 18 A
Max r
DS(on)
= 5.2 mΩ at V
GS
= 4.5 V, I
D
= 17 A
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET
TM
(Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
Notebook VCORE
MOSFET Maximum Ratings T
A
= 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Q1 Q2 Units
V
DS
Drain to Source Voltage 30 30 V
V
GS
Gate to Source Voltage (Note 3) ±20 ±12 V
I
D
Drain Current -Continuous (Package limited) T
C
= 25 °C 30 60
A
-Continuous (Silicon limited) T
C
= 25 °C 60 77
-Continuous T
A
= 25 °C 13
1a
18
1b
-Pulsed 40 60
E
AS
Single Pulse Avalanche Energy 33
4
21
5
mJ
P
D
Power Dissipation for Single Operation T
A
= 25 °C 2.2
1a
2.5
1b
W
Power Dissipation for Single Operation T
A
= 25 °C 1
1c
1
1d
T
J
, T
STG
Operating and Storage Junction Temperature Range -55 to +150 °C
R
θJA
Thermal Resistance, Junction to Ambient 57
1a
50
1b
°C/WR
θJA
Thermal Resistance, Junction to Ambient 125
1c
120
1d
R
θJC
Thermal Resistance, Junction to Case 2.9 2.8
Device Marking Device Package Reel Size Tape Width Quantity
22CF
21CD
FDMS3668S Power 56 13 ” 12 mm 3000 units
4
3
2
1
5
6
7
8
Q
1
Q
2
G1
D1
D1
D1
G2
S2
S2
S2
D1
PHASE
(S1/D2)
S2
S2
S2
G2
D1
D1
D1
G1
Top
PHASE
Pin 1
Pin 1
Power 56
Bottom

Summary of content (16 pages)