Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS3669S, MOSFET

FDMS3669S PowerTrench

Power Stage

FDMS3669S Rev.C1

www.fairchildsemi.com

January 2013

FDMS3669S

PowerTrench

Power Stage

Asymmetric Dual N-Channel MOSFET

Features

Q1: N-Channel

 Max r

DS(on)

= 10 mΩ at V

= 10 V, I

= 13 A

 Max r

DS(on)

= 14.5 mΩ at V

= 4.5 V, I

= 10 A

Q2: N-Channel

 Max r

DS(on)

= 5 mΩ at V

= 10 V, I

= 18 A

 Max r

DS(on)

= 5.2 mΩ at V

= 4.5 V, I

= 17 A

 Low inductance packaging shortens rise/fall times, resulting in

lower switching losses

 MOSFET integration enables optimum layout for lower circuit

inductance and reduced switch node ringing

 RoHS Compliant

General Description

This device includes two specialized N-Channel MOSFETs in a

dual PQFN package. The switch node has been internally

connected to enable easy placement and routing of synchronous

buck converters. The control MOSFET (Q1) and synchronous

SyncFET

(Q2) have been designed to provide optimal power

efficiency.

Applications

 Computing

 Communications

 General Purpose Point of Load

 Notebook VCORE

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 30 30 V

Gate to Source Voltage (Note 3) ±20 ±12 V

Drain Current -Continuous (Package limited) T

= 25 °C 24 60

-Continuous (Silicon limited) T

= 25 °C 43 75

-Continuous T

= 25 °C 13

-Pulsed (Note 6) 50 60

Single Pulse Avalanche Energy 61

Power Dissipation for Single Operation T

= 25 °C 2.2

2.5

Power Dissipation for Single Operation T

= 25 °C 1.0

1.0

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient 57

°C/WR

θJA

Thermal Resistance, Junction to Ambient 125

120

θJC

Thermal Resistance, Junction to Case 5.0 2.8

Device Marking Device Package Reel Size Tape Width Quantity

9ACF

21CD

FDMS3669S Power 56 13 ” 12 mm 3000 units

Power 56

PHASE

(S1/D2)

Top

Bottom

PHASE

Pin 1

Summary of content (16 pages)

PAGE 1
PowerTrench® Power Stage Asymmetric Dual N-Channel MOSFET Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a Max rDS(on) = 10 mΩ at VGS = 10 V, ID = 13 A dual PQFN package. The switch node has been internally Max rDS(on) = 14.5 mΩ at VGS = 4.5 V, ID = 10 A connected to enable easy placement and routing of synchronous buck converters.
PAGE 2
Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1 Q2 1 500 μA μA IGSS Gate to Source Leakage Current VGS = 20 V, VDS= 0 V VGS = 12 V, VDS= 0 V Q1 Q2 100 100 nA nA 2.7 2.
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q1 Q2 Q2 0.8 0.7 0.8 0.7 1.2 1.2 1.2 1.2 V Q1 Q2 24 21 38 33 ns Q1 Q2 8 16 15 31 nC Drain-Source Diode Characteristics VSD VGS = 0 V, IS = 13 A V = 0 V, IS = 2 A Source to Drain Diode Forward Voltage GS VGS = 0 V, IS = 18 A VGS = 0 V, IS = 2 A trr Reverse Recovery Time Qrr Reverse Recovery Charge Q1: IF = 13 A, di/dt = 100 A/μs Q2: IF = 18 A, di/dt = 300 A/μs (Note 2) (Note 2) (Note 2) (Note 2) Notes: 1.
PAGE 4
5 VGS = 10 V VGS = 6 V 40 VGS = 4.5 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 50 VGS = 4 V 30 20 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.5 1.0 1.5 VGS = 3.5 V 2.0 2.5 VGS = 3.5 V 3 1 0 0 10 rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.
PAGE 5
2000 ID = 13 A 1000 Ciss 8 VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD =15 V VDD = 20 V 4 Coss 100 2 0 0 3 6 9 12 15 10 0.1 18 Figure 7. Gate Charge Characteristics 10 30 Figure 8. Capacitance vs Drain to Source Voltage 25 50 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) 20 TJ = 25 oC 15 TJ = 125 oC TJ = 100 oC 10 5 40 VGS = 10 V 30 VGS = 4.5 V 20 Limited by Package 10 o RθJC = 5.
PAGE 6
2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W (Note 1c) 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDMS3669S Rev.C1 6 www.fairchildsemi.
PAGE 7
25 oC unlenss otherwise noted 60 8 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V VGS = 4.5 V 45 VGS = 3.5 V VGS = 3 V 30 VGS = 2.5 V 15 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.3 0.6 0.9 1.2 6 4 VGS = 3.5 V VGS = 3 V 2 VGS = 4.5 V 0 1.5 0 15 30 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 14. On-Region Characteristics 45 60 20 ID = 18 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.
PAGE 8
10000 ID = 17 A Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 10 V 6 VDD = 15 V 4 VDD = 20 V 1000 Coss 100 2 0 f = 1 MHz VGS = 0 V 0 10 20 10 0.1 30 1 30 Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 80 ID, DRAIN CURRENT (A) 100 IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 100 oC 10 TJ = 25 oC TJ = 125 oC 60 0.01 0.1 1 10 100 VGS = 10 V VGS = 4.
PAGE 9
NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 0.01 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 SINGLE PULSE t2 o RθJA = 120 C/W 1E-3 1E-4 -4 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA (Note 1d) -3 10 -2 10 -1 0 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDMS3669S Rev.C1 9 www.fairchildsemi.
PAGE 10
SyncFETTM Schottky body diode Characteristics Fairchild’s SyncFETTM process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3669S. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device.
PAGE 11
1. Switch Node Ringing Suppression Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. Competitors solution Power Stage Device Figure 29.
PAGE 12
FDMS3669S PowerTrench® Power Stage Figure 30. Shows the Power Stage in a buck converter topology 2. Recommended PCB Layout Guidelines As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance.
PAGE 13
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application. 2.
PAGE 14
FDMS3669S PowerTrench® Power Stage Dimensional Outline and Pad Layout (2X ) CL B PKG CL 8 A 0.00 0.10 C 4.00 2.00 5.10 4.90 8 5 7 6 1.27 TYP 0.65 TYP 5 0.63 2.52 1.60 KEEP OUT AREA 2.15 6.25 5.90 PKG CL 0.00 CL 4.16 1.21 2.13 1 PIN # 1 INDICATOR 4 0.10 C (2 X) 0.63 1.18 TOP VIEW 2 1 SEE DETAIL A 3 4 2.31 3.15 0.59 3.18 5.10 RECOMMENDED LAND PATTERN FOR SAWN / PUNCHED TYPE SIDE VIEW 0.1 0 0.0 5 0.65 0.38 0.35 0.30 3.16 2.80 1 2 3 (6X) C A B C 0.70 0.
PAGE 15
FDMS3669S PowerTrench® Power Stage Dimensional Outline and Pad Layout 5.10 4.90 0.10 C (2X) SEE DETAIL B PKG C L 8 0.35 0.15 5 0.28 0.08 PKG 6.25 5.90 CL 1 4 DETAIL 'B' (SCALE: 2X) 0.10 C (2X) 0.41 (8X) 0.21 TOP VIEW 10? 5.90 5.70 5.00 4.80 SEE DETAIL C 0.10 C 0.35 0.15 8X 0.08 C C SIDE VIEW 1.10 0.90 0.35 0.30 (6X) 0.65 0.38 3.16 2.80 1 2 3 0.70 0.36 4 0.10 0.05 C A B C 1.34 1.
PAGE 16
tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.