Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS4435BZ, MOSFET

March 2011

FDMS4435BZ Rev.C3

www.fairchildsemi.com

FDMS4435BZ P-Channel Power Trench

MOSFET

FDMS4435BZ

P-Channel PowerTrench

MOSFET

-30 V, -18 A, 20 mΩ

Features

 Max r

DS(on)

= 20 mΩ at V

= -10 V, I

= -9.0 A

 Max r

DS(on)

= 37 mΩ at V

= -4.5 V, I

= -6.5 A

 Extended V

GSS

range (-25 V) for battery applications

 High performance trench technology for extremely low r

DS(on)

 High power and current handling capability

 HBM ESD protection level >7 kV typical (Note 4)

 100% UIL tested

 Termination is Lead-free and RoHS Compliant

General Description

This P-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced Power Trench

process that has

been especially tailored to minimize the on-state resistance. This

device is well suited for Power Management and load

switching applications common in Notebook Computers and

Portable Battery Packs.

Applications

 High side in DC-DC Buck Converters

 Notebook battery power management

 Load switch in Notebook

Bottom

Power 56

Top

Pin 1

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage -30 V

Gate to Source Voltage ±25 V

Drain Current -Continuous (Package limited) T

= 25 °C -18

-Continuous (Silicon limited) T

= 25 °C -35

-Continuous T

= 25 °C (Note 1a) -9.0

-Pulsed -50

Single Pulse Avalanche Energy (Note 3) 18 mJ

Power Dissipation T

= 25 °C 39

Power Dissipation T

= 25 °C (Note 1a) 2.5

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 3.2

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 50

Device Marking Device Package Reel Size Tape Width Quantity

FDMS4435BZ FDMS4435BZ Power 56 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
P-Channel PowerTrench® MOSFET -30 V, -18 A, 20 mΩ Features General Description Max rDS(on) = 20 mΩ at VGS = -10 V, ID = -9.0 A Max rDS(on) = 37 mΩ at VGS = -4.5 V, ID = -6.5 A This P-Channel MOSFET is produced using Fairchild Semiconductor’s advanced Power Trench® process that has been especially tailored to minimize the on-state resistance. This device is well suited for Power Management and load switching applications common in Notebook Computers and Portable Battery Packs.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = -250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = -250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V -1 μA IGSS Gate to Source Leakage Current VGS = ±25 V, VDS = 0 V ±10 μA -3.
PAGE 3
50 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 4.0 -ID, DRAIN CURRENT (A) VGS = -10 V VGS = -6 V 40 VGS = -4.5 V VGS = -4 V 30 20 VGS = -3.5 V 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 VGS = -3.5 V VGS = -4 V 3.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 3.0 2.0 VGS = -6 V 1.5 1.0 VGS = -10 V 0.5 4 0 10 20 30 -ID, DRAIN CURRENT (A) -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.
PAGE 4
-VGS, GATE TO SOURCE VOLTAGE (V) 10 5000 ID = -9 A 8 Ciss CAPACITANCE (pF) VDD = -10 V 6 VDD = -15 V 4 VDD = -20 V 1000 Coss 2 0 0 8 16 24 32 100 0.1 40 1 Figure 7. Gate Charge Characteristics 30 Figure 8. Capacitance vs Drain to Source Voltage 20 40 -ID, DRAIN CURRENT (A) -IAS, AVALANCHE CURRENT (A) 10 -VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 32 VGS = -10 V 24 16 VGS = -4.5 V Package Limited 8 o RθJC = 3.2 C/W 1 0.01 0.
PAGE 5
P(PK), PEAK TRANSIENT POWER (W) 1000 100 10 SINGLE PULSE o RθJA = 125 C/W o 1 TA = 25 C 0.5 -4 10 -3 10 -2 -1 10 10 1 100 10 1000 t, PULSE WIDTH (sec) Figure 13. Single Pulse Maximum Power Dissipation 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.
PAGE 6
FDMS4435BZ P-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2011 Fairchild Semiconductor Corporation FDMS4435BZ Rev.C3 6 www.fairchildsemi.
PAGE 7
tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.