Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS7600AS, MOSFET

FDMS7600AS Dual N-Channel PowerTrench

MOSFET

FDMS7600AS Rev.C1

www.fairchildsemi.com

May 2014

FDMS7600AS

Dual N-Channel PowerTrench

MOSFET

N-Channel: 30 V, 30 A, 7.5 mΩ N-Channel: 30 V, 40 A, 2.8 mΩ

Features

Q1: N-Channel

 Max r

DS(on)

= 7.5 mΩ at V

= 10 V, I

= 12 A

 Max r

DS(on)

= 12 mΩ at V

= 4.5 V, I

= 10 A

Q2: N-Channel

 Max r

DS(on)

= 2.8 mΩ at V

= 10 V, I

= 20 A

 Max r

DS(on)

= 3.3 mΩ at V

= 4.5 V, I

= 18 A

 RoHS Compliant

General Description

This device includes two specialized N-Channel MOSFETs in a

dual MLP package.The switch node has been internally

connected to enable easy placement and routing of synchronous

buck converters. The control MOSFET (Q1) and synchronous

SyncFET

(Q2) have been designed to provide optimal power

efficiency.

Applications

 Computing

 Communications

 General Purpose Point of Lo

 Notebook V

CORE

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 30 30 V

Gate to Source Voltage (Note 3) ±20 ±20 V

Drain Current -Continuous T

= 25 °C 30 40

A -Continuous T

= 25 °C 12

-Pulsed 40 60

Power Dissipation for Single Operation T

= 25 °C 2.2

2.5

= 25 °C 1.0

1.0

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient 57

°C/WR

θJA

Thermal Resistance, Junction to Ambient 125

120

θJC

Thermal Resistance, Junction to Case 3.5 2

Device Marking Device Package Reel Size Tape Width Quantity

FDMS7600AS FDMS7600AS Power 56 13 ” 12 mm 3000 units

Power 56

S1/D2

Top

Bottom

Summary of content (12 pages)

PAGE 1
FDMS7600AS Dual N-Channel PowerTrench® MOSFET N-Channel: 30 V, 30 A, 7.5 mΩ N-Channel: 30 V, 40 A, 2.8 mΩ Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 12 A dual MLP package.The switch node has been internally Max rDS(on) = 12 mΩ at VGS = 4.5 V, ID = 10 A connected to enable easy placement and routing of synchronous buck converters.
PAGE 2
Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 1 mA, referenced to 25 °C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1 Q2 1 500 μA μA IGSS Gate to Source Leakage Current VGS = 20 V, VDS= 0 V Q1 Q2 100 100 nA nA 3 3 V V 15 18 mV/°C On Charact
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 0.7 1.2 1.2 V Q1 Q2 27 47 43 75 ns Q1 Q2 10 80 18 128 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 12 A VGS = 0 V, IS = 20 A (Note 2) (Note 2) Q1 IF = 12 A, di/dt = 100 A/μs Q2 IF = 20 A, di/dt = 300 A/μs Notes: 1: RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in.
PAGE 4
0 4 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V VGS = 6 V 30 VGS = 4.5 V VGS = 4 V 20 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3.5 V 0 0.0 0.5 1.0 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 3 VGS = 3.5 V VGS = 4 V 2 VGS = 4.5 V 1 VGS = 6 V 0 2.0 0 Figure 1. On Region Characteristics 30 40 40 ID = 12 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.
PAGE 5
VGS, GATE TO SOURCE VOLTAGE (V) 10 2000 ID = 12 A 1000 Ciss 8 CAPACITANCE (pF) VDD = 10 V 6 VDD = 15 V 4 VDD = 20 V Coss 100 2 Crss f = 1 MHz VGS = 0 V 0 0 5 10 15 10 0.1 20 Figure 7. Gate Charge Characteristics 10 30 Figure 8. Capacitance vs Drain to Source Voltage 100 60 o RθJC = 3.5 C/W 100us ID, DRAIN CURRENT (A) VGS = 10 V ID, DRAIN CURRENT (A) 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) 40 VGS = 4.5 V 20 Limited by Package 10 1 ms 1 0.
PAGE 6
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 SINGLE PULSE t2 o NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA RθJA = 125 C/W (Note 1c) 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMS7600AS Rev.C1 6 www.fairchildsemi.
PAGE 7
25 oC unlenss otherwise noted 60 3 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V ID, DRAIN CURRENT (A) VGS = 6 V 40 VGS = 4.5 V VGS = 3.5 V VGS = 3 V 20 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.1 0.2 0.3 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 3.5 V VGS = 4.5 V VGS = 6 V VGS = 10 V 1 0 0 20 40 60 ID, DRAIN CURRENT (A) Figure 14. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 10 ID = 20 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.
PAGE 8
10000 10 VGS, GATE TO SOURCE VOLTAGE (V) ID = 20A Ciss CAPACITANCE (pF) 8 VDD = 10 V 6 VDD = 15 V 4 VDD = 20 V Coss 1000 2 f = 1 MHz VGS = 0 V 0 30 60 Crss 100 0.1 0 90 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 20. Capacitance vs Drain to Source Voltage Figure 19. Gate Charge Characteristics 150 100 o RθJC = 2 C/W ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = 10 V 120 90 VGS = 4.5 V 60 30 Limited by Package 0 25 50 10 1 0.
PAGE 9
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 TJ = 25 oC unless otherwise noted DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 120 C/W (Note 1d) 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure24. Junction-to-Ambient Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMS7600AS Rev.C1 9 www.fairchildsemi.
PAGE 10
SyncFETTM Schottky body diode Characteristics Fairchild’s SyncFETTM process embeds a Schottky diode in parallel with PowerTrench® MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 25 shows the reverse recovery characteristic of the FDMS7600AS. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device.
PAGE 11
5.00 0.05 C B A 2X 4.46 1.27 8 0.65 6 7 5 0.63(5X) 0.25 6.00 0.40 2.67 6.30 0.54 0.66 0.05 C PIN#1 IDENT 2X 0.92 0.10 C 1 0.08 C SIDE VIEW C SEATING PLANE 2 0.65 (5X) 2 3 4 4.00 RECOMMENDED LAND PATTERN (OPTION 1 - FUSED LEADS 5,6,7) (0.34)4X 1 3 4.46 1.27 4 PIN#1 IDENT 8 0.65(8X) 6 7 5 0.63(8X) 0.40 (0.66) 2.67 6.30 0.54 0.66 0.45 8 0.10 C A B 0.05 C 6 7 0.92 5 1.27 BOTTOM VIEW NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. B.
PAGE 12
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