Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS7650, MOSFET

January 2012

FDMS7650 Rev.D3

www.fairchildsemi.com

FDMS7650 N-Channel PowerTrench

MOSFET

FDMS7650

N-Channel PowerTrench

MOSFET

30 V, 100 A, 0.99 mΩ

Features

 Max r

DS(on)

= 0.99 mΩ at V

= 10 V, I

= 36 A

 Max r

DS(on)

= 1.55 mΩ at V

= 4.5 V, I

= 32 A

 Advanced Package and Silicon combination for low r

DS(on)

and high efficiency

 MSL1 robust package design

 100% UIL tested

 RoHS Compliant

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency and to minimize switch node

ringing of DC/DC converters using either synchronous or

conventional switching PWM controllers. It has been optimized

for low gate charge and extremely low r

DS(on)

Applications

 OringFET

 Synchronous rectifier

Bottom

Top

Pin 1

Power 56

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 30 V

Gate to Source Voltage (Note 4) ±20 V

Drain Current -Continuous (Package limited) T

= 25 °C 100

-Continuous (Silicon limited) T

= 25 °C 232

-Continuous T

= 25 °C (Note 1a) 36

-Pulsed 200

Single Pulse Avalanche Energy (Note 3) 544 mJ

Power Dissipation T

= 25 °C 104

Power Dissipation T

= 25 °C (Note 1a) 2.5

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 1.2

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 50

Device Marking Device Package Reel Size Tape Width Quantity

FDMS7650 FDMS7650 Power 56 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMS7650 N-Channel PowerTrench® MOSFET 30 V, 100 A, 0.99 mΩ Features General Description Advanced Package and Silicon combination for low rDS(on) and high efficiency This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge and extremely low rDS(on).
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V 100 nA 3 V 30 V 15 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Th
PAGE 3
200 7 ID, DRAIN CURRENT (A) 160 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 10 V VGS = 4.5 V 120 VGS = 4 V 80 VGS = 3.5 V 40 VGS = 3 V 0 0 0.5 1.0 1.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 6 VGS = 3 V 5 4 VGS = 3.5 V 3 VGS = 4 V 2 1 VGS = 4.5 V 2.0 0 40 VDS, DRAIN TO SOURCE VOLTAGE (V) 120 160 200 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 rDS(on), DRAIN TO 1.4 1.2 1.0 0.
PAGE 4
VGS, GATE TO SOURCE VOLTAGE (V) 10 20000 ID = 36 A 10000 Ciss CAPACITANCE (pF) 8 VDD = 10 V 6 VDD = 15 V 4 VDD = 20 V Coss 1000 2 Crss f = 1 MHz VGS = 0 V 100 0.1 0 0 40 80 120 160 Qg, GATE CHARGE (nC) 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 300 100 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o RθJC = 1.2 C/W TJ = 25 oC 10 TJ = 125 oC 1 -3 10 -2 -1 10 10 1 10 2 200 VGS = 4.
PAGE 5
2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMS7650 Rev.D3 5 www.fairchildsemi.
PAGE 6
FDMS7650 N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2012 Fairchild Semiconductor Corporation FDMS7650 Rev.D3 6 www.fairchildsemi.
PAGE 7
tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.