Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS7692A, MOSFET

June 2009

FDMS7692A Rev.B

www.fairchildsemi.com

FDMS7692A N-Channel PowerTrench

MOSFET

FDMS7692A

N-Channel PowerTrench

MOSFET

30 V, 8 mΩ

Features

 Max r

DS(on)

= 8 mΩ at V

= 10 V, I

= 13 A

 Max r

DS(on)

= 14 mΩ at V

= 4.5 V, I

= 10 A

 Advanced Package and Silicon combination for low r

DS(on)

and high efficiency

 Next generation enhanced body diode technology, engineered

for soft recovery.

 MSL1 robust package design

 100% UIL tested

 RoHS Compliant

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency and to minimize switch node

ringing of DC/DC converters using either synchronous or

conventional switching PWM controllers. It has been optimized

for low gate charge, low r

DS(on),

fast switching speed and body

diode reverse recovery performance.

Applications

 IMVP Vcore Switching for Notebook

 VRM Vcore Switching for Desktop and Server

 OringFET / Load Switch

 DC-DC Conversion

Bottom

Power 56

Top

Pin 1

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 30 V

Gate to Source Voltage ±20 V

Drain Current -Continuous (Package limited) T

= 25 °C 28

-Continuous (Silicon limited) T

= 25 °C 45

-Continuous T

= 25 °C (Note 1a) 13.5

-Pulsed 50

Single Pulse Avalanche Energy (Note 3) 21 mJ

Power Dissipation T

= 25 °C 27

Power Dissipation T

= 25 °C (Note 1a) 2.5

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 4.6

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 50

Device Marking Device Package Reel Size Tape Width Quantity

FDMS7692A FDMS7692A Power 56 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMS7692A N-Channel PowerTrench® MOSFET 30 V, 8 mΩ Features General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A Max rDS(on) = 14 mΩ at VGS = 4.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 µA, VGS = 0 V ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 µA IGSS Gate to Source Leakage Current, Forward VGS = 20 V, VDS = 0 V 100 nA 3.
PAGE 3
VGS = 10 V ID, DRAIN CURRENT (A) 40 VGS = 4.5 V VGS = 4.0 V 30 VGS = 3.5 V 20 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 10 VGS = 3.0 V 0 0.0 10 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 50 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 6 VGS = 3.5 V 4 VGS = 4.0 V 2 VGS = 4. 5 V 0 0.5 1.0 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 2.0 20 VGS = 10 V 30 40 50 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 1.5 rDS(on), DRAIN TO 1.4 1.3 1.2 1.1 1.0 0.9 0.
PAGE 4
2000 ID = 13 A 1000 8 VDD = 15 V 6 VDD = 10 V Ciss CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 20 V 4 Coss 100 2 0 0 4 8 12 10 0.1 16 1 Figure 7. Gate Charge Characteristics 30 Figure 8. Capacitance vs Drain to Source Voltage 50 ID, DRAIN CURRENT (A) 50 IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 40 30 VGS = 10 V 20 Limited by Package VGS = 4.5 V 10 o RθJC = 4.6 C/W 1 0.001 0.01 0.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -4 10 -3 -2 10 -1 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve Figure 15. 14 12 CURRENT (A) 10 8 di/dt = 300 A/µs 6 4 2 0 -2 0 20 40 60 80 100 TIME (ns) Figure 14.
PAGE 6
FDMS7692A N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2009 Fairchild Semiconductor Corporation FDMS7692A Rev.B 6 www.fairchildsemi.
PAGE 7
tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.