Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS8320L, MOSFET

June 2012

FDMS8320L Rev.C3

www.fairchildsemi.com

FDMS8320L N-Channel PowerTrench

MOSFET

FDMS8320L

N-Channel PowerTrench

MOSFET

40 V, 100 A, 1.1 mΩ

Features

 Max r

DS(on)

= 1.1 mΩ at V

= 10 V, I

= 32 A

 Max r

DS(on)

= 1.5 mΩ at V

= 4.5 V, I

= 27 A

 Advanced Package and Silicon combination for low r

DS(on)

and high efficiency

 Next generation enhanced body diode technology,

engineered for soft recovery

 MSL1 robust package design

 100% UIL tested

 RoHS Compliant

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency and to minimize switch node

ringing of DC/DC converters using either synchronous or

conventional switching PWM controllers.It has been optimized

for low gate charge, low r

DS(on)

, fast switching speed ang body

diode reverse recovery performance.

Applications

 OringFET / Load Switching

 Synchronous Rectification

 DC-DC Conversion

Power 56

Pin 1

Bottom

Top

Pin 1

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 40 V

Gate to Source Voltage ±20 V

Drain Current -Continuous (Package limited) T

= 25 °C 100

-Continuous (Silicon limited) T

= 25 °C 238

-Continuous T

= 25 °C (Note 1a) 36

-Pulsed 150

Single Pulse Avalanche Energy (Note 3) 264 mJ

Power Dissipation T

= 25 °C 104

Power Dissipation T

= 25 °C (Note 1a) 2.5

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 1.2

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 50

Device Marking Device Package Reel Size Tape Width Quantity

FDMS8320L FDMS8320L Power 56 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMS8320L N-Channel PowerTrench® MOSFET 40 V, 100 A, 1.1 mΩ Features General Description Max rDS(on) = 1.1 mΩ at VGS = 10 V, ID = 32 A Max rDS(on) = 1.5 mΩ at VGS = 4.5 V, ID = 27 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V 100 nA 3.
PAGE 3
120 ID, DRAIN CURRENT (A) 5 VGS = 10 V VGS = 4.5 V VGS = 4 V VGS = 3.5 V VGS = 3 V 90 60 30 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 0.2 0.4 0.6 0.8 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 150 4 VGS = 3 V 3 VGS = 3.5 V 2 1 VGS = 4 V 0 1.0 0 30 Figure 1. On Region Characteristics 90 120 150 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 5 ID = 32 A VGS = 10 V 1.5 rDS(on), DRAIN TO 1.4 1.3 1.2 1.1 1.
PAGE 4
30000 ID = 32 A 10000 8 Ciss VDD = 20 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 16 V VDD = 24 V 4 Coss 1000 100 2 0 0 25 50 75 100 10 0.1 125 1 40 Figure 8. Capacitance vs Drain to Source Voltage 200 240 100 200 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) Figure 7. Gate Charge Characteristics TJ = 25 oC TJ = 100 oC 10 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 125 oC VGS = 10 V 160 VGS = 4.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve FDMS8320L Rev.C3 5 www.fairchildsemi.
PAGE 6
FDMS8320L N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout FDMS8320L Rev.C3 6 www.fairchildsemi.
PAGE 7
tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.