Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS8333L, MOSFET

April 2013

FDMS8333L Rev. C2

www.fairchildsemi.com

FDMS8333L N-Channel PowerTrench

MOSFET

FDMS8333L

N-Channel PowerTrench

MOSFET

40 V, 76 A, 3.1 mΩ

Features

 Max r

DS(on)

= 3.1 mΩ at V

= 10 V, I

= 22 A

 Max r

DS(on)

= 4.3 mΩ at V

= 4.5 V, I

= 19 A

 Advanced Package and Silicon combination for low r

DS(on)

and high efficiency

 Next generation enhanced body diode technology,

engineered for soft recovery

 MSL1 robust package design

 100% UIL tested

 RoHS Compliant

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency and to minimize switch node

ringing of DC/DC converters using either synchronous or

conventional switching PWM controllers. It has been optimized

for low gate charge, low r

DS(on)

, fast switching speed and body

diode reverse recovery performance.

Applications

 OringFET / Load Switching

 Synchronous rectification

 DC-DC Conversion

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 40 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 76

A -Continuous T

= 25 °C (Note 1a) 22

-Pulsed (Note 4) 250

Single Pulse Avalanche Energy (Note 3) 216 mJ

Power Dissipation T

= 25 °C 69

Power Dissipation T

= 25 °C (Note 1a) 2.5

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 1.8

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 50

Device Marking Device Package Reel Size Tape Width Quantity

FDMS8333L FDMS8333L Power 56 13 ’’ 12 mm 3000 units

Power 56

Pin 1

Bottom

Top

Pin 1

Summary of content (7 pages)

PAGE 1
FDMS8333L N-Channel PowerTrench® MOSFET 40 V, 76 A, 3.1 mΩ Features General Description Max rDS(on) = 3.1 mΩ at VGS = 10 V, ID = 22 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. Max rDS(on) = 4.3 mΩ at VGS = 4.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 3.
PAGE 3
5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 250 VGS = 10 V 200 VGS = 4.5 V VGS = 4 V 150 VGS = 3.5 V 100 VGS = 3 V 50 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 VGS = 3 V 4 VGS = 3.5 V 3 VGS = 4 V 2 VGS = 4.5 V 1 0 5 0 50 VDS, DRAIN TO SOURCE VOLTAGE (V) 150 200 250 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 15 ID = 22 A VGS = 10 V rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.6 -75 SOURCE ON-RESISTANCE (mΩ) 1.
PAGE 4
5000 ID = 22 A Ciss 8 VDD = 15 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 20 V 4 VDD = 25 V 1000 Coss 100 2 Crss f = 1 MHz VGS = 0 V 0 0 10 20 30 40 10 0.1 50 1 10 40 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 140 100 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 1.8 C/W TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 1 0.01 0.01 0.
PAGE 5
NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.01 t1 0.001 0.0001 -4 10 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDMS8333L Rev. C2 5 www.fairchildsemi.
PAGE 6
5.10 4.90 A PKG CL 8 5.10 3.91 B 5 8 7 6 1.27 5 0.77 4.52 PIN #1 IDENT MAY APPEAR AS OPTIONAL 1 KEEP OUT AREA 3.75 6.25 5.90 PKG CL 6.61 1.27 TOP VIEW 4 1 2 3 4 0.61 1.27 SEE DETAIL A 3.81 LAND PATTERN RECOMMENDATION SIDE VIEW 5.10 4.90 3.81 OPTIONAL DRAFT ANGLE MAY APPEAR ON FOUR SIDES OF THE PACKAGE 1.27 1 2 3 6 0.46 (8X) 0.36 0.10 C A B (0.39) 4 (0.52) 0.71 0.44 CHAMFER CORNER AS PIN #1 IDENT MAY APPEAR AS OPTIONAL 6.25 5.90 (0.50) (1.81) (3.40) 4.29 4.09 (1.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.