Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS86101A, MOSFET

April 2012

FDMS86101A Rev.C

www.fairchildsemi.com

FDMS86101A N-Channel PowerTrench

MOSFET

FDMS86101A

N-Channel PowerTrench

MOSFET

100 V, 60 A, 8 mΩ

Features

 Max r

DS(on)

= 8 mΩ at V

= 10 V, I

= 13 A

 Max r

DS(on)

= 13.5 mΩ at V

= 6 V, I

= 9.5 A

 Advanced Package and Silicon combination for low r

DS(on)

and high efficiency

 MSL1 robust package design

 100% UIL tested

 100% Rg tested

 RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor‘s advanced Power Trench

process thant has

been especially tailored to minimize the on-state resistance and

yet maintain superior switching performance.

Application

 DC-DC Conversion

Power 56

Pin 1

Bottom

Top

Pin 1

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 100 V

Gate to Source Voltage ±20 V

Drain Current -Continuous (Package limited) T

= 25 °C 60

-Continuous (Silicon limited) T

= 25 °C 81

-Continuous T

= 25 °C (Note 1a) 13

-Pulsed 180

Single Pulse Avalanche Energy (Note 3) 486 mJ

Power Dissipation T

= 25 °C 104

Power Dissipation T

= 25 °C (Note 1a) 2.5

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 1.2

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 50

Device Marking Device Package Reel Size Tape Width Quantity

FDMS86101A FDMS86101A Power 56 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMS86101A N-Channel PowerTrench® MOSFET 100 V, 60 A, 8 mΩ Features General Description This N-Channel MOSFET is produced using Fairchild Semiconductor‘s advanced Power Trench® process thant has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A Max rDS(on) = 13.5 mΩ at VGS = 6 V, ID = 9.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 800 nA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4.
PAGE 3
ID, DRAIN CURRENT (A) VGS = 10 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 180 VGS = 6 V 150 VGS = 5.5 V 120 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 90 VGS = 5 V 60 VGS = 4.5 V 30 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 5.5 V 2 VGS = 6 V 1 VGS = 10 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 30 60 90 120 150 180 ID, DRAIN CURRENT (A) Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 40 ID = 13 A VGS = 10 V 1.8 rDS(on), DRAIN TO 1.6 1.4 1.
PAGE 4
10000 VDD = 50 V ID = 13 A Ciss 8 VDD = 25 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 75 V 6 4 1000 Coss 100 2 10 0 0 5 10 15 20 25 30 35 40 Crss f = 1 MHz VGS = 0 V 5 0.1 45 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 100 90 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 1.2 C/W TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 1 0.01 0.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMS86101A Rev.C 5 www.fairchildsemi.
PAGE 6
5.10 4.90 A PKG CL 8 5.10 3.91 B 5 8 7 6 1.27 5 0.77 4.52 PIN #1 IDENT MAY APPEAR AS OPTIONAL 1 KEEP OUT AREA 3.75 6.25 5.90 PKG CL 6.61 1.27 TOP VIEW 4 1 2 3 4 0.61 1.27 SEE DETAIL A 3.81 LAND PATTERN RECOMMENDATION SIDE VIEW 5.10 4.90 3.81 OPTIONAL DRAFT ANGLE MAY APPEAR ON FOUR SIDES OF THE PACKAGE 1.27 1 2 3 6 0.46 (8X) 0.36 0.10 C A B (0.39) 4 (0.52) 0.71 0.44 CHAMFER CORNER AS PIN #1 IDENT MAY APPEAR AS OPTIONAL 6.25 5.90 (0.50) (1.81) (3.40) 4.29 4.09 (1.
PAGE 7
tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.