Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS86101DC, MOSFET

July 2013

FDMS86101DC Rev. C4

www.fairchildsemi.com

FDMS86101DC N-Channel Dual Cool

Shielded Gate PowerTrench

MOSFET

FDMS86101DC

N-Channel Dual Cool

Shielded Gate PowerTrench

MOSFET

100 V, 60 A, 7.5 mΩ

Features

 Shielded Gate MOSFET Technology

 Dual Cool

Top Side Cooling PQFN package

 Max r

DS(on)

= 7.5 mΩ at V

= 10 V, I

= 14.5 A

 Max r

DS(on)

= 12 mΩ at V

= 6 V, I

= 11.5 A

 High performance technology for extremely low r

DS(on)

 100% UIL Tested

 RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced PowerTrench

process that

incorporates Shielded Gate technology. Advancements in both

silicon and Dual Cool

package technologies have been

combined to offer the lowest r

DS(on)

while maintaining excellent

switching performance by extremely low Junction-to-Ambient

thermal resistance.

Applications

 Primary DC-DC MOSFET

 Secondary Synchronous Rectifier

 Load Switch

Bottom

Top

Pin 1

Power 56

Pin 1

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 100 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 60

A -Continuous T

= 25 °C (Note 1a) 14.5

-Pulsed 200

Single Pulse Avalanche Energy (Note 3) 216 mJ

Power Dissipation T

= 25 °C 125

Power Dissipation T

= 25 °C (Note 1a) 3.2

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case (Top Source) 2.3

°C/W

θJC

Thermal Resistance, Junction to Case (Bottom Drain) 1.0

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 38

θJA

Thermal Resistance, Junction to Ambient (Note 1b) 81

θJA

Thermal Resistance, Junction to Ambient (Note 1i) 16

θJA

Thermal Resistance, Junction to Ambient (Note 1j) 23

θJA

Thermal Resistance, Junction to Ambient (Note 1k) 11

Device Marking Device Package Reel Size Tape Width Quantity

86101 FDMS86101DC Dual Cool

Power 56 13’’ 12 mm 3000 units

Summary of content (8 pages)

PAGE 1
FDMS86101DC N-Channel Dual CoolTM Shielded Gate PowerTrench® MOSFET 100 V, 60 A, 7.5 mΩ Features General Description Shielded Gate MOSFET Technology High performance technology for extremely low rDS(on) This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that incorporates Shielded Gate technology.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25°C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4 V 100 V 70 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source
PAGE 3
RθJC Thermal Resistance, Junction to Case (Top Source) 2.3 RθJC Thermal Resistance, Junction to Case (Bottom Drain) 1.
PAGE 4
5 VGS = 8 V VGS = 10 V ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 200 VGS = 7 V VGS = 6 V 150 100 VGS = 5 V 50 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 5 VGS = 5 V 4 VGS = 6 V 3 VGS = 7 V 2 1 0 0 50 100 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics 200 25 ID = 14.5 A VGS = 10 V 2.0 rDS(on), DRAIN TO 1.8 1.6 1.4 1.2 1.0 0.8 0.
PAGE 5
000 ID = 14.5 A Ciss VDD = 25 V 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 50 V 6 VDD = 75 V 4 1000 Coss 100 2 f = 1 MHz VGS = 0 V 0 0 8 16 24 1 Figure 7. Gate Charge Characteristics 100 Figure 8. Capacitance vs Drain to Source Voltage 100 TJ ID, DRAIN CURRENT (A) 90 = 25 oC 10 TJ = 100 oC TJ = 125 oC 75 60 VGS = 10 V 45 VGS = 6 V Limited by Package 30 15 o RθJC = 1.0 C/W 1 0.001 0.01 0.
PAGE 6
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 81 C/W 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDMS86101DC Rev. C4 6 www.fairchildsemi.
PAGE 7
FDMS86101DC N-Channel Dual CoolTM Shielded Gate PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2013 Fairchild Semiconductor Corporation FDMS86101DC Rev. C4 7 www.fairchildsemi.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.