Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS86150, MOSFET

November 2013

FDMS86150 Rev.C3

www.fairchildsemi.com

FDMS86150 N-Channel Shielded Gate PowerTrench

MOSFET

Bottom

Power 56

Top

Pin 1

FDMS86150

N-Channel Shielded Gate PowerTrench

MOSFET

100 V, 80 A, 4.85 mΩ

Features

 Shielded Gate MOSFET Technology

 Max r

DS(on)

= 4.85 mΩ at V

= 10 V, I

= 16 A

 Max r

DS(on)

= 7.8 mΩ at V

= 6 V, I

= 13 A

 Advanced Package and Silicon combination for low r

DS(on)

and high efficiency

 MSL1 robust package design

 100% UIL tested

 RoHS Compliant

General Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor‘s advanced PowerTrench

process that

incorporates Shielded Gate technology. This process has been

optimized for the on-state resistance and yet maintain superior

switching performance.

Applications

 Primary DC-DC MOSFET

 Secondary Synchronous Rectifier

 Load Switch

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 100 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 80

A -Continuous T

= 25 °C (Note 1a) 16

-Pulsed 300

Single Pulse Avalanche Energy (Note 3) 726 mJ

Power Dissipation T

= 25 °C 156

Power Dissipation T

= 25 °C (Note 1a) 2.7

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 0.8

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 45

Device Marking Device Package Reel Size Tape Width Quantity

FDMS86150 FDMS86150 Power 56 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMS86150 N-Channel Shielded Gate PowerTrench® MOSFET 100 V, 80 A, 4.85 mΩ Features General Description This N-Channel MOSFET is produced using Fairchild Semiconductor‘s advanced PowerTrench® process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. Shielded Gate MOSFET Technology Max rDS(on) = 4.85 mΩ at VGS = 10 V, ID = 16 A Max rDS(on) = 7.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4 V 100 V 72 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source
PAGE 3
250 ID, DRAIN CURRENT (A) 4 VGS = 10 V VGS = 8 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 300 VGS = 7 V 200 150 VGS = 6 V 100 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 50 VGS = 5 V 0 0 1 2 3 4 VGS = 5 V 3 VGS = 6 V VGS = 7 V 2 1 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 5 0 50 VDS, DRAIN TO SOURCE VOLTAGE (V) 150 200 250 300 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 20 ID = 16 A VGS = 10 V 2.0 rDS(on), DRAIN TO 1.8 1.6 1.4 1.2 1.0 0.8 0.
PAGE 4
VGS, GATE TO SOURCE VOLTAGE (V) 10 10000 ID = 16 A VDD = 50 V VDD = 25 V CAPACITANCE (pF) 8 VDD = 75 V 6 4 Ciss 1000 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 10 0.1 0 0 10 20 30 40 50 1 Figure 7. Gate Charge Characteristics 125 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 100 Figure 8. Capacitance vs Drain to Source Voltage 100 TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 1 100 VGS = 10 V 75 Limited by Package 50 VGS = 6 V 25 o RθJC = 0.8 C/W 0.1 0.01 0.
PAGE 5
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: ZθJA(t) = r(t) x RθJA 0.01 SINGLE PULSE 0.001 -3 10 RθJA = 115 °C/W Peak TJ = PDM x ZθJA(t) + TA Duty Cycle, D = t1 / t2 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMS86150 Rev.C3 5 www.fairchildsemi.
PAGE 6
FDMS86150 N-Channel Shielded Gate PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2012 Fairchild Semiconductor Corporation FDMS86150 Rev.C3 6 www.fairchildsemi.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.