Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS86300, MOSFET

October 2012

FDMS86300 Rev.C1

www.fairchildsemi.com

FDMS86300 N-Channel PowerTrench

MOSFET

FDMS86300

N-Channel PowerTrench

MOSFET

80 V, 80 A, 3.9 mΩ

Features

 Max r

DS(on)

= 3.9 mΩ at V

= 10 V, I

= 19 A

 Max r

DS(on)

= 5.5 mΩ at V

= 8 V, I

= 15.5 A

 Advanced Package and Silicon combination for low r

DS(on)

and high efficiency

 Next generation enhanced body diode technology,

engineered for soft recovery

 MSL1 robust package design

 100% UIL tested

 RoHS Compliant

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency and to minimize switch node

ringing of DC/DC converters using either synchronous or

conventional switching PWM controllers.It has been optimized

for low gate charge, low r

DS(on)

, fast switching speed and body

diode reverse recovery performance.

Applications

 OringFET / Load Switching

 DC-DC Conversion

Power 56

Pin 1

Bottom

Top

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 80 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 80

A -Continuous T

= 25 °C (Note 1a) 19

-Pulsed (Note 4) 250

Single Pulse Avalanche Energy (Note 3) 252 mJ

Power Dissipation T

= 25 °C 104

Power Dissipation T

= 25 °C (Note 1a) 2.5

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 1.2

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 50

Device Marking Device Package Reel Size Tape Width Quantity

FDMS86300 FDMS86300 Power 56 13 ’’ 12 mm 3000 units

Summary of content (7 pages)

PAGE 1
N-Channel PowerTrench® MOSFET 80 V, 80 A, 3.9 mΩ Features General Description Max rDS(on) = 3.9 mΩ at VGS = 10 V, ID = 19 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers.It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. Max rDS(on) = 5.5 mΩ at VGS = 8 V, ID = 15.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 64 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4.
PAGE 3
250 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 5 VGS = 8 V VGS = 7 V 200 VGS = 6.5 V VGS = 10 V 150 VGS = 6 V 100 VGS = 5.5 V 50 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 5 VGS = 5.5 V 4 VGS = 6 V VGS = 6.5 V 3 VGS = 7 V 2 VGS = 8 V 1 0 0 50 Figure 1. On-Region Characteristics 200 250 12 ID = 19 A VGS = 10 V rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 150 Figure 2.
PAGE 4
10000 ID = 19 A Ciss VDD = 40 V 8 VDD = 30 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 50 V 6 4 1000 Coss 100 10 2 Crss f = 1 MHz VGS = 0 V 0 0 10 20 30 40 50 60 70 1 0.1 80 1 Figure 7. Gate Charge Characteristics 140 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 80 Figure 8. Capacitance vs Drain to Source Voltage 100 TJ = 25 oC TJ = 100 oC 10 TJ = 125 oC 120 100 80 VGS = 10 V 60 Limited by Package VGS = 8 V 40 20 o RθJC = 1.2 C/W 1 0.01 0.
PAGE 5
NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 0.01 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE 0.001 o RθJA = 125 C/W 0.0001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMS86300 Rev.C1 5 www.fairchildsemi.
PAGE 6
FDMS86300 N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2012 Fairchild Semiconductor Corporation FDMS86300 Rev.C1 6 www.fairchildsemi.
PAGE 7
tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.