Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS86520L, MOSFET

May 2014

FDMS86520L Rev.C1

www.fairchildsemi.com

FDMS86520L N-Channel PowerTrench

MOSFET

FDMS86520L

N-Channel PowerTrench

MOSFET

60 V, 22 A, 8.2 mΩ

Features

 Max r

DS(on)

= 8.2 mΩ at V

= 10 V, I

= 13.5 A

 Max r

DS(on)

= 11.7 mΩ at V

= 4.5 V, I

= 11.5 A

 Advanced package and silicon combination for low r

DS(on)

and

high efficiency

 MSL1 robust package design

 100% UIL tested

 RoHS Compliant

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency and to minimize switch node

ringing of DC/DC converters using either synchronous or

conventional switching PWM controllers. It has been optimized

for low gate charge, low r

DS(on)

, fast switching speed and body

diode reverse recovery performance.

Applications

 Primary Switch in isolated DC-DC

 Synchronous Rectifier

 Load Switch

Power 56

Pin 1

Bottom

Top

MOSFET Maximum Ratings T

= 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

Drain to Source Voltage 60 V

Gate to Source Voltage ±20 V

Drain Current -Continuous T

= 25 °C 22

A -Continuous T

= 25 °C (Note 1a) 13.5

-Pulsed 60

Single Pulse Avalanche Energy (Note 3) 91 mJ

Power Dissipation T

= 25 °C 69

Power Dissipation T

= 25 °C (Note 1a) 2.5

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case 1.8

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 50

Device Marking Device Package Reel Size Tape Width Quantity

FDMS86520L FDMS86520L Power 56 13 ’’ 12

mm 3000 units

Summary of content (7 pages)

PAGE 1
FDMS86520L N-Channel PowerTrench® MOSFET 60 V, 22 A, 8.2 mΩ Features General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. Max rDS(on) = 8.2 mΩ at VGS = 10 V, ID = 13.5 A Max rDS(on) = 11.7 mΩ at VGS = 4.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 48 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 3 V 60 V 29 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source
PAGE 3
60 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 50 ID, DRAIN CURRENT (A) 5 VGS = 10 V VGS = 4.5 V VGS = 3.5 V VGS = 4 V 40 30 20 VGS = 3 V 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.5 1.0 1.5 2.0 VGS = 3 V 4 VGS = 3.5 V 3 VGS = 4 V 2 1 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 10 20 30 40 50 60 ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.8 40 ID = 13.
PAGE 4
10000 ID = 13.5 A Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 30 V 6 VDD = 20 V VDD = 40 V 4 1000 Coss 100 Crss 10 2 f = 1 MHz VGS = 0 V 0 0 5 10 15 20 25 30 35 40 1 0.1 45 1 Figure 7. Gate Charge Characteristics 80 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 60 VGS = 10 V 40 VGS = 4.5 V 20 o Limited by Package 1 0.001 0.01 0.1 1 10 0 25 100 50 100 125 150 Figure 10.
PAGE 5
2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMS86520L Rev.C1 5 www.fairchildsemi.
PAGE 6
FDMS86520L N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout 5.20 4.90 A PKG CL 8 B 5 0.35 0.15 SEE DETAIL B 0.30 0.10 6.25 5.90 PKG CL 5.85 5.65 DETAIL B 1 SCALE: 2:1 4 TOP VIEW OPTIONAL DRAFT ANGLE MAY APPEAR ON FOUR SIDES OF THE PACKAGE 5.00 4.80 SEE DETAIL C 0.10 C 0.05 0.00 8X SIDE VIEW 0.08 C 1.10 0.90 3.81 1.27 0.51 (8X) 0.31 2 3 0.10 C A B 4 0.76 0.44 NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR.
PAGE 7
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.