Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDMS9620S, MOSFET

May 2014

FDMS9620S Dual N-Channel PowerTrench

MOSFET

FDMS9620S Rev.D3

www.fairchildsemi.com

FDMS9620S

Dual N-Channel PowerTrench

MOSFET

Q1: 30V, 16A, 21.5m:Q2: 30V, 18A, 13m:

Features

Q1: N-Channel

 Max r

DS(on)

= 21.5m: at V

= 10V, I

= 7.5A

 Max r

DS(on)

= 29.5m: at V

= 4.5V, I

= 6.5A

Q2: N-Channel

 Max r

DS(on)

= 13m: at V

= 10V, I

= 10A

 Max r

DS(on)

= 17m: at V

= 4.5V, I

= 8.5A

 Low Qg high side MOSFET

 Low r

DS(on)

low side MOSFET

 Thermally efficient dual Power 56 package

 Pinout optimized for simple PCB design

 RoHS Compliant

General Description

This device includes two specialized MOSFETs in a unique dual

Power 56 package. It is designed to provide an optimal

Synchronous Buck power stage in terms of efficiency and PCB

utilization. The low switching loss "High Side" MOSFET is

complemented by a Low Conduction Loss "Low Side" SyncFET.

Applications

Synchronous Buck Converter for:

 Notebook System Power

 General Purpose Point of Load

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 30 30 V

Gate to Source Voltage ±20 ±20 V

= 25°C 16 18

-Continuous T

= 25°C (Note 1a) 7.5 10

-Pulsed 60 60

Power Dissipation for Single Operation T

= 25°C (Note 1a) 2.5

= 25°C (Note 1b) 1

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

TJC

Thermal Resistance, Junction to Case 8.2 3.1

°C/WR

TJA

Thermal Resistance, Junction to Ambient (Note 1a) 50

TJA

Thermal Resistance, Junction to Ambient (Note 1b) 120

Device Marking Device Package Reel Size Tape Width Quantity

FDMS9620S FDMS9620S Power 56 13” 12mm 3000 units

Power 56

S1/D2

Drain Current -Continuous T

Summary of content (9 pages)

PAGE 1
FDMS9620S Dual N-Channel PowerTrench® MOSFET Q1: 30V, 16A, 21.5m: Q2: 30V, 18A, 13m: Features Q1: N-Channel General Description Max rDS(on) = 21.5m: at VGS = 10V, ID = 7.5A Max rDS(on) = 29.5m: at VGS = 4.5V, ID = 6.5A This device includes two specialized MOSFETs in a unique dual Q2: N-Channel Synchronous Buck power stage in terms of efficiency and PCB Max rDS(on) = 13m: at VGS = 10V, ID = 10A utilization. Max rDS(on) = 17m: at VGS = 4.5V, ID = 8.
PAGE 2
Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250PA, VGS = 0V ID = 1mA, VGS = 0V Q1 Q2 'BVDSS 'TJ Breakdown Voltage Temperature Coefficient ID = 250PA, referenced to 25°C ID = 1mA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24V, VGS = 0V Q1 Q2 1 500 PA IGSS Gate to Source Leakage Current VGS = ±20V, VDS= 0V Q1 Q2 ±100 ±100 nA 3 3 V V 23 23 mV/°C On Characteristics VGS
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units 2.1 3.5 A 1.2 1.0 V Drain-Source Diode Characteristics IS Maximum Continuous Drain-Source Diode Forward Current VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0V, IS = 2.1A VGS = 0V, IS = 3.5A Q1 IF = 7.5A, di/dt = 100A/Ps Q2 IF = 10A, di/dt = 300A/Ps Q1 Q2 (Note 2) (Note 2) Q1 Q2 0.7 0.
PAGE 4
60 VGS = 6V 50 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 2.8 VGS = 10V VGS = 4.5V 40 VGS = 4V 30 VGS = 3.5V 20 PULSE DURATION = 300Ps DUTY CYCLE = 2.0%MAX 10 0 0 1 2 3 PULSE DURATION = 300Ps DUTY CYCLE = 2.0%MAX 2.6 2.4 2.2 VGS =3.5V VGS = 4V 2.0 VGS = 6V 1.6 1.4 1.2 1.0 VGS = 10V 0.8 4 0 10 20 VDS, DRAIN TO SOURCE VOLTAGE (V) rDS(on), DRAIN TO 1.3 1.2 1.1 1.0 0.9 0.
PAGE 5
1000 ID = 7.5A VDD =10V 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE(V) 10 VDD = 15V 6 VDD = 20V 4 Ciss Coss 100 2 f = 1MHz VGS = 0V 0 0 2 4 6 8 10 30 0.1 12 Figure 7. Gate Charge Characteristics P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 100 10 1ms SINGLE PULSE TJ = MAX RATE 10ms RTJA = 120oC 100ms TA = 25oC 1s THIS AREA IS LIMITED BY rDS(ON) 0.01 0.1 10s DC 1 10 30 Figure 8. Capacitance vs Drain to Source Voltage 100 0.
PAGE 6
0 ID, DRAIN CURRENT (A) VGS = 4V VGS = 4.5V 50 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 2.8 VGS = 10V VGS = 6V 40 VGS = 3.5V 30 20 10 PULSE DURATION = 300Ps DUTY CYCLE = 2.0%MAX 0 0.0 0.5 1.0 1.5 2.0 2.5 2.6 PULSE DURATION = 300Ps DUTY CYCLE = 2.0%MAX VGS =3.5V 2.4 2.2 VGS = 4V 2.0 1.6 VGS = 6V 1.4 1.2 1.0 VGS = 10V 0.8 0 10 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 40 50 60 Figure 13. Normalized on-Resistance vs Drain Current and Gate Voltage 1.
PAGE 7
2000 ID = 10A VDD =10V VDD = 15V 6 4 Ciss 1000 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE(V) 10 VDD = 20V 2 Coss 100 50 0.1 0 0 4 8 12 16 20 Crss 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) Figure 19. Capacitance vs Drain to Source Voltage Figure 18. Gate Charge Characteristics ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 f = 1MHz VGS = 0V 7 www.fairchildsemi.
PAGE 8
5.00 0.05 C B A 2X 4.42 4.00 1.27 8 6.00 7 0.61(8X) 6 5 0.63(8X) 0.40 2.67 0.05 C PIN#1 IDENT 2X 4.25 0.54 6.30 0.66 0.92 0.10 C 0.40 0.08 C SIDE VIEW C SEATING PLANE 1 2 3 4 RECOMMENDED LAND PATTERN NOTES: (0.34)4X 2 1 3 4 A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. PIN#1 IDENT B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. (0.66) D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. E.
PAGE 9
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