Datasheet

March 1998
FDN337N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
Absolute Maximum Ratings T
A
= 25
o
C unless other wise noted
Symbol Parameter FDN337N Units
V
DSS
Drain-Source Voltage 30 V
V
GSS
Gate-Source Voltage - Continuous ±8 V
I
D
Drain/Output Current - Continuous 2.2 A
- Pulsed 10
P
D
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
0.46
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
FDN337N Rev.C
2.2 A, 30 V, R
DS(ON)
= 0.065 Ω @ V
GS
= 4.5 V
R
DS(ON)
= 0.082 Ω @ V
GS
= 2.5 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOT
TM
-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SuperSOT
TM
-3 N-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
G
D
S
SuperSOT -3
TM
337
D
S
G
© 1998 Fairchild Semiconductor Corporation