FDP038AN06A0 / FDI038AN06A0 N-Channel PowerTrench® MOSFET 60 V, 80 A, 3.8 mΩ Features Applications • RDS(on) = 3.5 mΩ ( Typ.) @ VGS = 10 V, ID = 80 A • Synchronous Rectification for ATX / Server / Telecom PSU • QG(tot) = 96 nC ( Typ.
Device Marking FDP038AN06A0 Device FDP038AN06A0 Package TO-220 Reel Size Tube Tape Width N/A Quantity 50 units FDI038AN06A0 FDI038AN06A0 I2-PAK Tube N/A 50 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit 60 - - - V - 1 - - 250 µA VGS = ±20V - - ±100 nA - 4 V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µ
1.2 250 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 200 150 100 50 0.2 0 0 25 50 75 100 150 125 0 25 175 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 o TC, CASE TEMPERATURE ( C) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.
2000 100 10µs 1000 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 10ms 1 DC SINGLE PULSE TJ = MAX RATED TC = 25oC STARTING TJ = 25oC IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100µs STARTING TJ = 150oC 10 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 0.1 1 10 1 0.01 100 0.1 1 10 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5.
1.4 1.2 VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 0.2 -80 -40 0 40 80 120 160 1.1 1.0 0.9 200 -80 -40 TJ, JUNCTION TEMPERATURE (oC) Figure 11.
VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS VGS = 10V + Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 18. Gate Charge Waveforms Figure 17. Gate Charge Test Circuit VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS VGS 0 Figure 19.
.SUBCKT FDP038AN06A0 2 1 3 ; rev July 04, 2002 Ca 12 8 1.5e-9 Cb 15 14 1.5e-9 Cin 6 8 6.1e-9 LDRAIN DPLCAP DRAIN 2 5 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 69.
rev July 4, 2002 template FDP038AN06A0 n2,n1,n3 = m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=2.4e-11,nl=1.04,rs=1.65e-3,trs1=2.7e-3,trs2=2e-7,cjo=4.35e-9,m=5.4e-1,tt=1e-9,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.7e-9,isl=10e-30,nl=10,m=0.47) m..model mmedmod = (type=_n,vto=3.3,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.00,kp=275,is=1e-30, tox=1) LDRAIN m..model mweakmod = (type=_n,vto=2.72,kp=0.
th REV 23 July 4, 2002 JUNCTION FDP038AN06A0T CTHERM1 TH 6 6.45e-3 CTHERM2 6 5 3e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.65e-2 CTHERM5 3 2 4.85e-2 CTHERM6 2 TL 1e-1 RTHERM1 CTHERM1 6 RTHERM1 TH 6 3.24e-3 RTHERM2 6 5 8.08e-3 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 1e-1 RTHERM5 3 2 1.1e-1 RTHERM6 2 TL 1.4e-1 RTHERM2 CTHERM2 5 SABER Thermal Model RTHERM3 SABER thermal model FDP035AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =6.45e-3 ctherm.ctherm2 6 5 =3e-2 ctherm.ctherm3 5 4 =1.
FDP038AN06A0 / FDI038AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-220 3L Figure 21. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
FDP038AN06A0 / FDI038AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-262 3L (I2PAK) Figure 22. 3LD, TO262, Jedec Variation AA (I2PAK) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
