Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDP100N10, MOSFET

November 2013

FDP100N10 — N-Channel PowerTrench

MOSFET

FDP100N10 Rev. C3

www.fairchildsemi.com

FDP100N10

N-Channel PowerTrench

MOSFET

100 V, 75 A, 10 mΩ

Features

•R

DS(on)

= 8.2 mΩ (Typ.) @ V

= 10 V, I

= 75 A

• Fast Switching Speed

• Low Gate Charge

• High Performance Trench Technology for Extremely Low

DS(on)

• High Power and Current Handling Capability

• RoHS Compliant

Description

This N-Channel MOSFET is produced using Fairchild Semicon-

ductor’s advanced PowerTrench

process that has been tai-

lored to minimize the on-state resistance while maintaining

superior switching performance.

Applications

• Synchronous Rectification for ATX / Server / Telecom PSU

• Battery Protection Circuit

• Motor Drives and Uninterruptible Power Supplies

• Micor Solar Inverter

TO-220

MOSFET Maximum Ratings T

= 25

C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FDP100N10 Unit

DSS

Drain to Source Voltage 100 V

GSS

Gate to Source Voltage ±20 V

Drain Current - Continuous (T

= 75

C) 75 A

D r a i n C u r r e n t - P u l s e d (Note 1) 300 A

Single Pulsed Avalanche Energy (Note 2) 365 mJ

dv/dt Peak Diode Recovery dv/dt (Note 3) 6 V/ns

Power Dissipation

= 25

C) 208 W

- Derate Above 25

C1.4W/

, T

STG

Operating and Storage Temperature Range -55 to +175

Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds

300

Symbol Parameter FDP100N10 Unit

θJC

Thermal Resistance, Junction to Case, Max. 0.72

C/W

θJA

Thermal Resistance, Junction to Ambient, Max. 62.5

Summary of content (8 pages)

PAGE 1
FDP100N10 N-Channel PowerTrench® MOSFET 100 V, 75 A, 10 mΩ Features Description • RDS(on) = 8.2 mΩ (Typ.) @ VGS = 10 V, ID = 75 A This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that has been tailored to minimize the on-state resistance while maintaining superior switching performance.
PAGE 2
Part Number FDP100N10 Top Mark FDP100N10 Electrical Characteristics Symbol Package TO-220 Packing Method Tube Reel Size N/A Tape Width N/A Quantity 50 units TC = 25oC unless otherwise noted. Parameter Test Conditions Min. Typ. Max. Unit 100 - - V - 0.
PAGE 3
Figure 1. On-Region Characteristics VGS = 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V 100 ID,Drain Current[A] ID,Drain Current[A] 500 Figure 2. Transfer Characteristics 1000 10 100 o 150 C o -55 C o 25 C 10 *Notes: 1. 250μs Pulse Test *Notes: 1. VDS = 20V 2. 250μs Pulse Test o 2. TC = 25 C 5 0.1 1 1 VDS,Drain-Source Voltage[V] 5 Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 4 6 8 10 VGS,Gate-Source Voltage[V] 1000 IS, Reverse Drain Current [A] 0.
PAGE 4
Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 3.0 1.1 1.0 0.9 *Notes: 1. VGS = 0V 2. ID = 250μA 0.8 -100 -50 0 50 100 150 o TJ, Junction Temperature [ C] 2.5 RDS(on), [Normalized] Drain-Source On-Resistance BVDSS, [Normalized] Drain-Source Breakdown Voltage 1.2 2.0 1.5 1.0 0.0 -100 200 500 100 100 80 100 μs 10 THIS AREA IS LIMITED BY rDS(on) SINGLE PULSE TJ = MAX RATED 1 ms Tc = 25 oC 0.1 0.
PAGE 5
FDP100N10 — N-Channel PowerTrench® MOSFET IG = const. Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS VDD VGS VGS DUT V 10V GS 90% 10% td(on) tr t on td(off) tf t off Figure 13. Resistive Switching Test Circuit & Waveforms VGS Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms ©2007 Fairchild Semiconductor Corporation FDP100N10 Rev. C3 5 www.fairchildsemi.
PAGE 6
FDP100N10 — N-Channel PowerTrench® MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15.
PAGE 7
FDP100N10 — N-Channel PowerTrench® MOSFET Mechanical Dimensions Figure 16. TO-220, Molded, 3-Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.