FDP16AN08A0 N-Channel PowerTrench® MOSFET 75 V, 58 A, 16 mΩ Features Applications • RDS(on) = 13 mΩ ( Typ.) @ VGS = 10 V, ID = 58 A • Synchronous Rectification for ATX / Server / Telecom PSU • QG(tot) = 28 nC ( Typ.
Device Marking Device Package Reel Size Tape Width Quantity FDP16AN08A0 FDP16AN08A0 TO-220 Tube N/A 50 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 75 - - - - 1 - - 250 VGS = ±20V - - ±100 nA VGS = VDS, ID = 250µA V ID = 29A, VGS = 6V V DS =
1.2 60 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 40 20 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (o C) Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 125 150 175 Figure 2. Maximum Continuous Drain Current vs Case Temperature DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 1 ZθJC, NORMALIZED THERMAL IMPEDANCE 100 TC, CASE TEMPERATURE (o C) PDM 0.
500 100 10µs IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 100µs 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms 1 DC SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 1 0.01 75 50 TJ = 175oC TJ = -55oC TJ = 25 C VGS = 10V VGS = 20V VGS = 7V 75 VGS = 6V 50 VGS = 5V 25 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VGS , GATE TO SOURCE VOLTAGE (V) 6.5 0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE(mΩ) 2.
1.4 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, I D = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + CGD C, CAPACITANCE (pF) 1.
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
.SUBCKT FDB16AN08A0 2 1 3 ; rev March 2002 Ca 12 8 10e-10 Cb 15 14 8e-10 Cin 6 8 1.7e-9 DPLCAP 10 RSLC2 + GATE 1 Lgate 1 9 5.96e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 5.75e-9 RLGATE EVTEMP RGATE + 18 22 9 20 ESLC 11 + 17 EBREAK 18 - 50 EVTHRES + 19 8 6 21 16 DBODY MWEAK MMED MSTRO CIN LSOURCE 8 7 RSOURCE RLgate 1 9 59.6 RLdrain 2 5 10 RLsource 3 7 57.5 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD DBREAK RDRAIN 6 8 ESG LGATE 5 51 - Ebreak 11 7 17 18 85.
rev March 2002 template FDB16AN08A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.4e-11,nl=1.08,rs=3.3e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=1.2e-9,m=5.6e-1,tt=1.3e-8,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=5e-10,isl=10e-30,nl=10,m=0.52) m..model mmedmod = (type=_n,vto=3.2,kp=4,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=3.85,kp=70,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.7,kp=0.06,is=1e-30, tox=1,rs=0.
th JUNCTION REV 23 March 2002 FDB16AN08A0T CTHERM1 th 6 0.002 CTHERM2 6 5 0.004 CTHERM3 5 4 0.006 CTHERM4 4 3 0.01 CTHERM5 3 2 0.03 CTHERM6 2 tl 0.08 RTHERM1 CTHERM1 6 RTHERM1 th 6 0.075 RTHERM2 6 5 0.09 RTHERM3 5 4 0.1 RTHERM4 4 3 0.15 RTHERM5 3 2 0.2 RTHERM6 2 tl 0.25 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDD16AN08A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 0.002 ctherm.ctherm2 6 5 = 0.004 ctherm.ctherm3 5 4 = 0.006 ctherm.ctherm4 4 3 = 0.
FDP16AN08A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-220 3L Figure 21. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
