FDP2552 N-Channel PowerTrench® MOSFET 150 V, 37 A, 36 mΩ Features Applications • RDS(on) = 32 mΩ ( Typ.) @ VGS = 10 V, ID = 16 A • Consumer Appliances • QG(tot) = 39 nC ( Typ.
Device Marking Device Package Reel Size Tape Width Quantity FDP2552 FDP2552 TO-220 Tube N/A 50 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 150 - - V - - 1 - - 250 µA VGS = ±20V - - ±100 nA V V DS = 120V VGS = 0V TC = 150oC On Characteristic
1.2 40 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 30 20 10 0.2 0 0 0 25 50 75 100 150 125 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.
100 300 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10µs 100µs IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms 1 SINGLE PULSE TJ = MAX RATED TC = 25oC DC STARTING TJ = 25 oC 10 STARTING TJ = 150o C 0.1 1 1 10 100 300 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5.
1.4 1.2 VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 0.9 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 4000 VGS , GATE TO SOURCE VOLTAGE (V) 10 CISS = CGS + CGD C, CAPACITANCE (pF) 1.0 0.8 -80 200 Figure 11.
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
rev May 2002 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 RSLC2 5 51 Ebreak 11 7 17 18 178 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 EVTHRES + 19 8 + LGATE GATE 1 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK ESLC - It 8 17 1 DRAIN 2 5 + .SUBCKT FDP2552 2 1 3 ; Ca 12 8 1e-9 Cb 15 14 1e-9 Cin 6 8 2.65e-9 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 7.
REV May 2002 template FDP2552 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.6e-11,nl=1.09,rs=2.6e-3,trs1=3.0e-3,trs2=1.5e-6,cjo=1.9e-9,m=0.62,tt=5.1e-8,xti=4.2) dp..model dbreakmod = (rs=0.3,trs1=3.0e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=5.7e-10,isl=10.0e-30,nl=10,m=0.58) m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.15,kp=80,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.91,kp=0.03,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..
th JUNCTION REV 23 May 2002 FDP2552T CTHERM1 TH 6 1e-2 CTHERM2 6 5 1.5e-2 CTHERM3 5 4 2e-2 CTHERM4 4 3 2.1e-2 CTHERM5 3 2 2.2e-2 CTHERM6 2 TL 9e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 2.7e-2 RTHERM2 6 5 2.8e-2 RTHERM3 5 4 7.8e-2 RTHERM4 4 3 9e-2 RTHERM5 3 2 2.7e-1 RTHERM6 2 TL 2.87e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDP2552T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =1e-2 ctherm.ctherm2 6 5 =1.5e-2 ctherm.ctherm3 5 4 =2e-2 ctherm.ctherm4 4 3 =2.
FDP2552 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-220 3L Figure 21. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
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