FDH3632 / FDP3632 / FDB3632 N-Channel PowerTrench® MOSFET 100 V, 80 A, 9 mΩ Features Applications • RDS(ON) = 7.5 mΩ (Typ.), VGS = 10 V, ID = 80 A • Synchronous Rectification • Qg(tot) = 84 nC (Typ.
Device Marking FDB3632 Device FDB3632 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units FDP3632 FDP3632 TO-220 FDH3632 FDH3632 TO-247 Tube N/A 50 units Tube N/A 30 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 100 - - - - 1 - -
125 CURRENT LIMITED BY PACKAGE 1.0 100 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 0 0 25 50 75 100 150 125 75 VGS = 10V 50 25 0 175 25 TC , CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE E - DESCE DING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.
00 200 10µs IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 100µs OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1ms 1 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC DC 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 STARTING TJ = 25oC STARTING TJ = 150oC 0.01 200 Figure 5. Forward Bias Safe Operating Area 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6.
1.4 1.2 VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 0.2 1.1 1.0 0.9 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 -80 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 Figure 12.
VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS VGS = 10V + Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 18. Gate Charge Waveforms Figure 17. Gate Charge Test Circuit VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS VGS 0 Figure 19.
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.
rev May 2002 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 RSLC2 5 51 Ebreak 11 7 17 18 102.5 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 EVTHRES + 19 8 + LGATE GATE 1 Lgate 1 9 5.61e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.7e-9 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK ESLC - It 8 17 1 DRAIN 2 5 + .SUBCKT FDB3632 2 1 3 ; CA 12 8 1.7e-9 Cb 15 14 2.5e-9 Cin 6 8 6.
REV May 2002 template FDB3632 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=5.9e-11,nl=1.07,rs=2.3e-3,trs1=3.0e-3,trs2=1.0e-6,cjo=4e-9,m=0.58,tt=4.8e-8,xti=4.2) dp..model dbreakmod = (rs=0.17,trs1=3.0e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=15e-10,isl=10.0e-30,nl=10,m=0.6) m..model mstrongmod = (type=_n,vto=4.1,kp=200,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=3.4,kp=10.0,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.75,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..
th JUNCTION REV May 2002 FDB3632 CTHERM1 TH 6 7.5e-3 CTHERM2 6 5 8.0e-3 CTHERM3 5 4 9.0e-3 CTHERM4 4 3 2.4e-2 CTHERM5 3 2 3.4e-2 CTHERM6 2 TL 6.5e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 3.1e-4 RTHERM2 6 5 2.5e-3 RTHERM3 5 4 2.2e-2 RTHERM4 4 3 8.1e-2 RTHERM5 3 2 1.35e-1 RTHERM6 2 TL 1.5e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDB3632 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =7.5e-3 ctherm.ctherm2 6 5 =8.0e-3 ctherm.ctherm3 5 4 =9.0e-3 ctherm.ctherm4 4 3 =2.
FDH3632 / FDP3632 / FDB3632 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-247 3L Figure 22. TO-247, Molded, 3 Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
FDH3632 / FDP3632 / FDB3632 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-220 3L Figure 23. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
FDH3632 / FDP3632 / FDB3632 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 24. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
