Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDP42AN15A0, MOSFET

November 2013

FDP42AN15A0 — N-Channel PowerTrench

MOSFET

www.fairchildsemi.com

FDP42AN15A0

Features

Formerly developmental type 82864

Applications

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

N-Channel PowerTrench

MOSFET

150 V, 35 A, 42 mΩ

DS(on)

= 36 mΩ ( Typ.) @ V

= 10 V, I

= 12 A

G(tot)

= 33 nC ( Typ.) @ V

= 10 V

Low Miller Charge

Low Q

Body Diode

UIS Capability (Single Pulse and Repetitive Pulse)

Consumer Appliances

Synchronous Rectification

Uninterruptible Power Supply

Micro Solar Inverter

•

TO-220

FDP42AN15A0 Rev. C2

Thermal Resistance, Junction to Case, Max. 1.0

Thermal Resistance, Junction to Ambient, Max. 62

Symbol Parameter FDP42AN15A0 Unit

DSS

Drain to Source Voltage 150 V

Gate to Source Voltage ±20 V

35 A

Drain Current

Continuous (T

= 25

10V)

Continuous (T

= 100

C, V

= 10V) 24

Continuous (T

= 25

C, V

= 10V, with R

θJA

= 43

C/W) 5 A

Pulsed Figure 4 A

Single Pulse Avalanche Energy (Note 1) 90 mJ

Power dissipation 150 W

Derate above 25

C1.00

CW/

, T

STG

Operating and Storage Temperature -55 to 175

Thermal Characteristics

θJC

C/W

θJA

C/W

Summary of content (11 pages)

PAGE 1
FDP42AN15A0 N-Channel PowerTrench® MOSFET 150 V, 35 A, 42 mΩ Features Applications • RDS(on) = 36 mΩ ( Typ.) @ VGS = 10 V, ID = 12 A • Consumer Appliances • QG(tot) = 33 nC ( Typ.
PAGE 2
Device Marking Device Package Reel Size Tape Width Quantity FDP42AN15A0 FDP42AN15A0 TO-220 Tube N/A 50 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit 150 - - - V - 1 - - 250 µA VGS = ±20V - - ±100 nA V Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V V DS = 120V VGS = 0V TC = 150oC On Characte
PAGE 3
1.2 40 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 150 125 30 20 10 0 175 25 50 75 TC , CASE TEMPERATURE (o C) Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 125 150 175 Figure 2. Maximum Continuous Drain Current vs Case Temperature DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 1 ZθJC, NORMALIZED THERMAL IMPEDANCE 100 TC, CASE TEMPERATURE (oC) PDM 0.
PAGE 4
100 200 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10µs 10 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 100µs OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 1 DC 10 100 10ms STARTING TJ = 25oC 10 STARTING TJ = 150 oC 1 0.001 300 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5.
PAGE 5
1.2 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, I D = 250µA 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE 160 VGS , GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 10 CISS = CGS + CGD COSS ≅ C DS + C GD CRSS = CGD 100 VGS = 0V, f = 1MHz 0.1 1.
PAGE 6
VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19.
PAGE 7
.SUBCKT FDB42AN15A0 2 1 3 ; rev June 11, 2002 Ca 12 8 6.0e-10 Cb 15 14 8e-10 Cin 6 8 2.1e-9 DPLCAP 10 RSLC2 + GATE 1 Lgate 1 9 4.81e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.63e-9 RLGATE EVTEMP RGATE + 18 22 9 20 ESLC 11 50 EVTHRES + 19 8 6 21 EBREAK 16 + 17 18 - DBODY MWEAK MMED MSTRO CIN LSOURCE 8 7 RSOURCE RLgate 1 9 48.1 RLdrain 2 5 10 RLsource 3 7 46.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD DBREAK RDRAIN 6 8 ESG LGATE 5 51 - Ebreak 11 7 17 18 159.
PAGE 8
rev June 11, 2002 template FDB42AN15A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.4e-11,nl=1.08,rs=4.2e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=1.35e-9,m=6.3e-1,tt=4.8e-8,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=.43e-9,isl=10e-30,nl=10,m=0.66) m..model mmedmod = (type=_n,vto=3.5,kp=4,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.0,kp=70,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.12,kp=0.06,is=1e-30, tox=1,rs=.
PAGE 9
th JUNCTION REV 23 June 11, 2002 FDB42AN15A0_Thermal CTHERM1 TH 6 2e-3 CTHERM2 6 5 4.5e-3 CTHERM3 5 4 7e-3 CTHERM4 4 3 3e-2 CTHERM5 3 2 4e-2 CTHERM6 2 TL 8.5e-1 RTHERM1 CTHERM1 6 RTHERM1 TH 6 6.2e-2 RTHERM2 6 5 8.2e-2 RTHERM3 5 4 9.2e-2 RTHERM4 4 3 9.7e-2 RTHERM5 3 2 0.2 RTHERM6 2 TL 0.22 RTHERM2 CTHERM2 5 SABER Thermal Model RTHERM3 SABER thermal model FDB42AN15A0_Thermal template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =2e-3 ctherm.ctherm2 6 5 =4.5e-3 ctherm.
PAGE 10
FDP42AN15A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-220 3L Figure 21. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 11
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.