Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDP5800, MOSFET

December 2013

FDP5800 — N-Channel Logic Level PowerTrench

MOSFET

FDP5800 Rev. C2

www.fairchildsemi.com

FDP5800

N-Channel Logic Level PowerTrench

MOSFET

60 V, 80 A, 6 mΩ

Features

•R

DS(on)

= 4.6 mΩ (Typ.) @ V

= 10 V, I

= 80 A

• High Performance Trench Technology for Extermly Low

DS(on)

• Low Gate Charge

• High Power and Current Handing Capability

•RoHS Compliant

Description

This N-Channel MOSFET is produced using Fairchild

Semiconductor’s advanced PowerTrench

process that has

been tailored to minimize the on-state resistance while main-

taining superior switching performance.

Applications

• Power Tools

• Motor Drives and Uninterruptible Power Supplies

• Synchronous Rectification

• Battery Protection Circuit

TO-220

MOSFET Maximum Ratings T

= 25°C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FDP5800 Unit

DSS

Drain-Source Voltage 60 V

GSS

Gate-Source Voltage ±20 V

D r a i n C u r r e n t

- Continuous (T

= 25

C) 80 A

- Continuous (T

= 100

C) A 80*

- Continuous (T

= 25

C) 14 A

Drain Current - Pulsed 320 A

Single Pulsed Avalanche Energy (Note 1) 652 mJ

Power Dissipation (T

= 25

- Derate Above 25

242

1.61

W/°C

, T

STG

Operating and Storage Temperature Range -55 to +175 °C

Symbol Parameter

FDP5800

Unit

θJC

Thermal Resistance, Junction to Case, Max. 0.62

C/W

θJA

Thermal Resistance, Junction to Ambient, Max. 62.5

*Drain current limited by package.

Summary of content (8 pages)

PAGE 1
FDP5800 N-Channel Logic Level PowerTrench® MOSFET 60 V, 80 A, 6 mΩ Features Description • RDS(on) = 4.6 mΩ (Typ.) @ VGS = 10 V, ID = 80 A This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that has been tailored to minimize the on-state resistance while maintaining superior switching performance.
PAGE 2
Part Number FDP5800 Top Mark FDP5800 Package TO-220 Packing Method Tube Reel Size N/A Tape Width N/A Quantity 50 units Electrical Characteristics TC= 25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max.
PAGE 3
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 1000 400 VDS = 6V * Notes : 1. 250μs Pulse Test o ID,Drain Current[A] ID,Drain Current[A] 2. TC = 25 C 100 VGS 10.0 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V Top : 10 5 0.03 0.1 1 VDS,Drain-Source Voltage[V] o 150 C 10 o 25 C 1 o -55 C 0.1 3 Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 1 IS, Reverse Drain Current [A] 1000 VGS = 10V 5.0 2 3 4 VGS,Gate-Source Voltage[V] 5 Figure 4.
PAGE 4
Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 2.4 rDS(on), [Normalized] Drain-Source On-Resistance BVDSS, [Normalized] Drain-Source Breakdown Voltage 1.2 1.1 1.0 0.9 0.8 -100 * Notes : 1. VGS = 0V 2. ID = 250μA -50 0 50 100 150 o TJ, Junction Temperature [ C] 0.8 * Notes : 1. VGS = 10V 2.
PAGE 5
FDP5800 — N-Channel Logic Level PowerTrench® MOSFET IG = const. Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS VDD VGS VGS DUT V 10V GS 90% 10% td(on) tr t on td(off) tf t off Figure 13. Resistive Switching Test Circuit & Waveforms VGS Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms ©2006 Fairchild Semiconductor Corporation FDP5800 Rev. C2 5 www.fairchildsemi.
PAGE 6
FDP5800 — N-Channel Logic Level PowerTrench® MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15.
PAGE 7
FDP5800 — N-Channel Logic Level PowerTrench® MOSFET Mechanical Dimensions Figure 16. TO-220, Molded, 3-Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.