Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDP61N20, MOSFET

November 2013

FDP61N20 — N-Channel UniFET

MOSFET

FDP61N20 Rev. C1

www.fairchildsemi.com

FDP61N20

N-Channel UniFET

MOSFET

200 V, 61 A, 41 mΩ

Features

•R

DS(on)

= 34 mΩ (Typ.) @ V

= 10 V, I

= 30.5 A

• Low Gate Charge (Typ. 58 nC)

•Low C

rss

(Typ. 80 pF)

• 100% Avalanche Tested

Applications

•PDP TV

• Lighting

• Uninterruptible Power Supply

• AC-DC Power Supply

Description

UniFET

MOSFET is Fairchild Semiconductor’s high voltage

MOSFET family based on planar stripe and DMOS technology.

This MOSFET is tailored to reduce on-state resistance, and to

provide better switching performance and higher avalanche

energy strength. This device family is suitable for switching

power converter applications such as power factor correction

(PFC), flat panel display (FPD) TV power, ATX and electronic

lamp ballasts.

TO-220

Absolute Maximum Ratings T

= 25°C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FDP61N20 Unit

DSS

Drain-Source Voltage 200 V

Drain Current - Continuous (T

= 25°C)

- Continuous (T

= 100°C)

38.5

Drain Current - Pulsed

(Note 1)

244 A

GSS

Gate-Source voltage ±30 V

Single Pulsed Avalanche Energy

(Note 2)

1440 mJ

Avalanche Current

(Note 1)

61 A

Repetitive Avalanche Energy

(Note 1)

41.7 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

4.5 V/ns

Power Dissipation (T

= 25°C)

- Derate Above 25°C

417

3.3

W/°C

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds 300 °C

Symbol Parameter FDP61N20 Unit

θJC

Thermal Resistance, Junction-to-Case, Max. 0.3

°C/W

θJA

Thermal Resistance, Junction-to-Ambient, Max. 62.5

Summary of content (8 pages)

PAGE 1
FDP61N20 N-Channel UniFETTM MOSFET 200 V, 61 A, 41 mΩ Features Description • RDS(on) = 34 mΩ (Typ.) @ VGS = 10 V, ID = 30.5 A UniFETTM MOSFET is Fairchild Semiconductor’s high voltage MOSFET family based on planar stripe and DMOS technology. This MOSFET is tailored to reduce on-state resistance, and to provide better switching performance and higher avalanche energy strength.
PAGE 2
Part Number Top Mark FDP61N20 FDP61N20 Electrical Characteristics Symbol Package TO-220 Packing Method Tube Reel Size N/A Tape Width N/A Quantity 50 units TC = 25°C unless otherwise noted. Parameter Conditions Min. Typ. Max. Unit 200 -- -- V Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 μA ΔBVDSS / ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, Referenced to 25°C -- 0.
PAGE 3
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics VGS Top : 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V ID, Drain Current [A] 10 2 10 ID, Drain Current [A] 2 1 10 o 150 C 1 10 o 25 C o -55 C ? Notes : 1. VDS = 40V ? Notes : 1. 250탎 Pulse Test 2. TC = 25? 2. 250탎 Pulse Test 0 0 10 -1 0 10 10 2 4 6 8 10 12 VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4.
PAGE 4
Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 3.0 RDS(ON), (Normalized) 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 150 Drain-Source On-Resistance BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 2.5 2.0 1.5 1.0 ? Notes : 1. VGS = 10 V 0.5 2. ID = 30.5 A 0.0 -100 200 -50 o 100 150 200 Figure 10. Maximum Drain Current vs.
PAGE 5
0KΩ 200nF 12V FDP61N20 — N-Channel UniFETTM MOSFET VGS Same Type as DUT Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on tf t off Figure 13. Resistive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG V 10V GS GS VDD ID (t) VDS (t) VDD DUT tp tp Time Figure 14.
PAGE 6
FDP61N20 — N-Channel UniFETTM MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15.
PAGE 7
FDP61N20 — N-Channel UniFETTM MOSFET Mechanical Dimensions Figure 16. TO-220, Molded, 3-Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.