Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDP8874, MOSFET

FDP8874 Rev. A3

FDP8874

N-Channel PowerTrench

MOSFET

30V, 114A, 5.3mΩ

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency of DC/DC converters using

either synchronous or conventional switching PWM

controllers. It has been optimized for low gate charge, low

DS(ON)

and fast switching speed.

Applications

• DC/DC converters

Features

•r

DS(ON)

= 5.3mΩ, V

= 10V, I

= 40A

•r

DS(ON)

= 6.6mΩ, V

= 4.5V, I

= 40A

• High performance trench technology for extremely low

DS(ON)

• Low gate charge

• High power and current handling capability

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

DSS

Drain to Source Voltage 30 V

Gate to Source Voltage ±20 V

Drain Current

114 A

Continuous (T

= 25

C, V

= 10V) (Note 1)

Continuous (T

= 25

C, V

= 4.5V) (Note 1) 102 A

Continuous (T

amb

= 25

C, V

= 10V, with R

θJA

= 62

C/W) 16 A

Pulsed Figure 4 A

Single Pulse Avalanche Energy (Note 2) 105 mJ

Power dissipation 110 W

Derate above 25

C0.73W/

, T

STG

Operating and Storage Temperature -55 to 175

θJC

Thermal Resistance Junction to Case TO-220 1.36

C/W

θJA

Thermal Resistance Junction to Ambient TO-220 ( Note 3) 62

C/W

Device Marking Device Package Reel Size Tape Width Quantity

FDP8874 FDP8874 TO-220AB Tube N/A 50 units

TO-220AB

FDP SERIES

DRAIN

GATE

SOURCE

(FLANGE)

tmM

May 2008

•

RoHS Compliant

Summary of content (10 pages)

PAGE 1
FDP8874 N May 2008 FDP8874 tmM N-Channel PowerTrench® MOSFET 30V, 114A, 5.3mΩ General Description Features This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed. • rDS(ON) = 5.3mΩ, VGS = 10V, ID = 40A • rDS(ON) = 6.6mΩ, VGS = 4.
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Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V VDS = 24V VGS = 0V TC = 150oC VGS = ±20V 30 - - V - - 1 - - 250 µA - - ±100 nA - 2.5 V On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250µA 1.2 ID = 40A, VGS = 10V - 0.0036 0.
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FDP8874 Typical Characteristics TC = 25°C unless otherwise noted 125 CURRENT LIMITED BY PACKAGE 1.0 100 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 75 VGS = 10V VGS = 4.5V 50 25 0.2 0 0 0 25 50 75 100 150 125 TC , CASE TEMPERATURE 175 25 50 75 (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Case Temperature Figure 2.
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FDP8874 Typical Characteristics TC = 25°C unless otherwise noted 500 1000 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10µs 100 100µs 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 1 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC DC 1 0.01 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 60 Figure 5.
PAGE 5
FDP8874 Typical Characteristics TC = 25°C unless otherwise noted 1.2 1.10 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250µA 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 1.05 1.00 0.95 0.90 -80 200 -40 TJ, JUNCTION TEMPERATURE (oC) 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature Figure 12.
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FDP8874 Test Circuits and Waveforms VDS BVDSS tP L VDS VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS = 10V VGS Qg(5) + Qgs2 VDD VGS = 5V DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18.
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.SUBCKT FDP8874 2 1 3 ; rev May 2004 Ca 12 8 2.3e-9 Cb 15 14 2.25e-9 Cin 6 8 2.9e-9 LDRAIN DPLCAP DRAIN 2 5 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 33.3 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 RLDRAIN RSLC1 51 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 8.
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FDP8874 SABER Electrical Model rev May 2004 template FDP8874 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=4.1e-12,ikf=10,nl=1.01,rs=2e-3,trs1=8e-4,trs2=2e-7,cjo=1.22e-9,m=0.57,tt=3e-12,xti=3) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.12e-9,isl=10e-30,nl=10,m=0.42) m..model mmedmod = (type=_n,vto=2,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.5,kp=390,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.72,kp=0.
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th FDP8874 PSPICE Thermal Model JUNCTION REV 23 May 2004 FDP8874T CTHERM1 TH 6 1.9e-3 CTHERM2 6 5 2.8e-3 CTHERM3 5 4 3.5e-3 CTHERM4 4 3 3.6e-3 CTHERM5 3 2 4.0e-3 CTHERM6 2 TL 1.6e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 3.8e-2 RTHERM2 6 5 5.0e-2 RTHERM3 5 4 1.0e-1 RTHERM4 4 3 1.8e-1 RTHERM5 3 2 3.5e-1 RTHERM6 2 TL 3.7e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDP8874T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =1.9e-3 ctherm.ctherm2 6 5 =2.8e-3 ctherm.
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