Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDS2572, MOSFET

FDS2572

SO-8

Pin 1

SO-8

FDS2572

150V, 0.047 Ohms, 4.9A, N-Channel UltraFET

Trench MOSFET

General Description

UltraFET

devices combine characteristics that enable

benchmark efficiency in power conversion applications.

Optimized for Rds(on), low ESR, low total and Miller gate

charge, these devices are ideal for high frequency DC to

DC converters.

Applications

• DC/DC converters

• Telecom and Data-Com Distributed Power Architectures

• 48-volt I/P Half-Bridge/Full-Bridge

• 24-volt Forward and Push-Pull topologies

Features

• R

DS(ON)

= 0.040Ω (Typ.), V

= 10V

• Q

g(TOT)

= 29nC (Typ.), V

= 10V

• Low Q

Body Diode

• Maximized efficiency at high frequencies

• UIS Rated

MOSFET Maximum Ratings T

=25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

DSS

Drain to Source Voltage 150 V

Gate to Source Voltage ±20 V

Drain Current

4.9 A

Continuous (T

= 25

C, V

= 10V, R

θJA

= 50

C/W)

Continuous (T

= 100

C, V

= 10V, R

θJA

= 50

3.1 A

Pulsed Figure 4 A

Power dissipation

Derate above 25

2.5

mW/

, T

STG

Operating and Storage Temperature -55 to 150

θJC

Thermal Resistance Junction to Case (NOTE1) 25

C/W

θJA

Thermal Resistance Junction to Case at 10 seconds (NOTE2) 50

C/W

θJA

Thermal Resistance Junction to Case at steady state (NOTE2) 85

C/W

Device Marking Device Reel Size Tape Width Quantity

FDS2572 FDS2572 330mm 12mm 2500units

July 2013

C/W)

Summary of content (12 pages)

PAGE 1
FDS2572 150V, 0.047 Ohms, 4.9A, N-Channel UltraFET® Trench MOSFET General Description Features ® UltraFET devices combine characteristics that enable benchmark efficiency in power conversion applications. Optimized for Rds(on), low ESR, low total and Miller gate charge, these devices are ideal for high frequency DC to DC converters. • RDS(ON) = 0.040Ω (Typ.), VGS = 10V Applications • • • • • Qg(TOT) = 29nC (Typ.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units 150 - - - V - 1 - - 250 µA - - ±100 Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V VDS = 120V VGS = 0V TC = 150o C VGS = ±20V nA On Characteristics VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 2 - 4 V rDS(ON) Drain to Source On Resistance ID = 4.9A, VGS = 10V - 0.040 0.
PAGE 3
FDS2572 Typical Characteristic POWER DISSIPATION MULTIPLIER 1.2 6 1.0 ID, DRAIN CURRENT (A) VGS = 10V 0.8 0.6 0.4 0.2 4 2 0 0 0 25 50 75 100 125 150 25 50 TA , AMBIENT TEMPERATURE (oC) 75 100 125 150 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continous Drain Current vs Case Temperature 2 THERMAL IMPEDANCE ZθJA, NORMALIZED 1 0.1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.
PAGE 4
FDS2572 Typical Characteristic (Continued) 30 IAS, AVALANCHE CURRENT (A) 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V ID , DRAIN CURRENT (A) STARTING TJ = 25oC STARTING TJ = 150oC 1 20 TJ = 25oC 10 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 0.1 0.001 0.1 1 10 tAV, TIME IN AVALANCHE (ms) TJ = 150oC TJ = -55oC 0 3 100 4 Figure 5. Unclamped Inductive Switching Capability 2.
PAGE 5
FDS2572 Typical Characteristic (Continued) 5000 10 VGS , GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) CISS = CGS + CGD 1000 COSS ≅ CDS + CGD CRSS = CGD 100 VGS = 0V, f = 1MHz 10 0.1 1 10 VDD = 75V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 4.9A ID = 1A 2 0 150 0 5 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 15 20 25 30 35 Qg, GATE CHARGE (nC) Figure 11. Capacitance vs Drain to Source Voltage Figure 12.
PAGE 6
FDS2572 Test Circuits and Waveforms (Continued) VDS tON tOFF td(OFF) td(ON) tf tr RL VDS 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 0 Figure 17. Switching Time Test Circuit ©2001 Fairchild Semiconductor Corporation 10% Figure 18. Switching Time Waveforms FDS2572 Rev.
PAGE 7
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
PAGE 8
.SUBCKT FDS2572 2 1 3 ; CA 12 8 8e-10 Cb 15 14 8e-10 Cin 6 8 2e-9 rev August 2001 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 Lgate 1 9 5.61e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.98e-9 EVTEMP RGATE + 18 22 9 20 21 EBREAK 16 + 17 18 - DBODY MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 19.
PAGE 9
REV August 2001 template FDS2572 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=4e-11,nl=1.131,rs=4.4e-3,trs1=2e-3,trs2=1e-6,cjo=1.44e-9,m=0.67,tt=7.4e-8,xti=4.2) dp..model dbreakmod = (rs=0.38,trs1=2e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=5e-10,isl=10e-30,nl=10,m=0.7) m..model mstrongmod = (type=_n,vto=4.05,kp=85,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=3.35,kp=5,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.76,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..
PAGE 10
th FDS2572 SPICE Thermal Model JUNCTION REV August 2001 FDS2572 Copper Area = 1 in2 CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2.0e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3 RTHERM1 CTHERM1 8 RTHERM2 CTHERM2 7 RTHERM1 TH 8 1.0e-1 RTHERM2 8 7 5.
PAGE 11
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE INCHES E E1 A MILLIMETERS SYMBOL A1 1 e NOTES 2 MIN MAX MIN MAX A 0.0532 0.0688 1.35 1.75 - A1 0.004 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 - c 0.0075 0.0098 0.19 0.25 - D 0.189 0.1968 4.80 5.00 2 E 0.2284 0.244 5.80 6.20 - E1 0.1497 0.1574 3.80 4.00 3 6 D 5 b h x 45o c 0.004 IN 0.10 mm L 0o-8o 0.060 1.52 e 0.050 BSC 1.27 BSC - H 0.0099 0.0196 0.25 0.50 - L 0.016 0.050 0.40 1.
PAGE 12
FDS2572 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.