Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDS8858CZ, MOSFET

October 2011

FDS8858CZ Dual N & P-Channel PowerTrench

MOSFET

FDS8858CZ Rev.C

www.fairchildsemi.com

FDS8858CZ

Dual N & P-Channel PowerTrench

MOSFET

N-Channel: 30V, 8.6A, 17.0mΩ P-Channel: -30V, -7.3A, 20.5mΩ

Features

Q1: N-Channel

 Max r

DS(on)

= 17mΩ at V

= 10V, I

= 8.6A

 Max r

DS(on)

= 20mΩ at V

= 4.5V, I

= 7.3A

Q2: P-Channel

 Max r

DS(on)

= 20.5mΩ at V

= -10V, I

= -7.3A

 Max r

DS(on)

= 34.5mΩ at V

= -4.5V, I

= -5.6A

 High power and handing capability in a widely used surface

mount package

 Fast switching speed

General Description

These dual N and P-Channel enhancement mode power

MOSFETs are produced using Fairchild Semiconductor’s

advanced PowerTrench process that has been especially

tailored to minimize on-state resistance and yet maintain

superior switching performance.

These devices are well suited for low voltage and battery

powered applications where low in-line power loss and fast

switching are required.

Applications

 Inverter

 Synchronous Buck

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 30 -30 V

Gate to Source Voltage ±20 ±25 V

Drain Current - Continuous T

= 25°C 8.6 -7.3

- Pulsed 20 -20

Single Pulse Avalanche Energy (Note 3) 50 11 mJ

Power Dissipation for Dual Operation 2.0

WPower Dissipation for Single Operation T

= 25°C (Note 1a) 1.6

= 25°C (Note 1c) 0.9

, T

STG

Operating and Storage Junction Temperature Range -55 to +150 °C

θJC

Thermal Resistance, Junction to Case (Note 1) 40

°C/W

θJA

Thermal Resistance, Junction to Ambient (Note 1a) 78

Device Marking Device Package Reel Size Tape Width Quantity

FDS8858CZ FDS8858CZ SO-8 13” 12mm 2500 units

Pin 1

SO-8

Summary of content (10 pages)

PAGE 1
FDS8858CZ Dual N & P-Channel PowerTrench® MOSFET N-Channel: 30V, 8.6A, 17.0mΩ P-Channel: -30V, -7.3A, 20.5mΩ Features General Description Q1: N-Channel These dual N and P-Channel enhancement Max rDS(on) = 17mΩ at VGS = 10V, ID = 8.6A MOSFETs are produced using Fairchild Semiconductor’s mode power advanced PowerTrench process that has been especially Max rDS(on) = 20mΩ at VGS = 4.5V, ID = 7.
PAGE 2
Symbol Parameter Test Conditions Type Min 30 -30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V ID = -250μA, VGS = 0V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250μA, referenced to 25°C ID = -250μA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24V, VGS = 0V VDS = -24V, VGS = 0V Q1 Q2 1 -1 μA IGSS Gate to Source Leakage Current VGS = ±20V, VDS = 0V VGS = ±25V, VDS = 0V Q1 Q2 ±10 ±10 μA 3
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 0.9 1.2 -1.2 V Q1 Q2 25 28 38 42 ns Q1 Q2 19 22 29 33 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0V, IS = 8.6A VGS = 0V, IS = -7.3A (Note 2) (Note 2) Q1 IF = 8.6A, di/dt = 100A/s Q2 IF = -7.3A, di/dt = 100A/s Notes: 1.
PAGE 4
3.0 20 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 16 ID, DRAIN CURRENT (A) PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX VGS = 10V VGS = 4.5V VGS = 3.5V 12 VGS = 3.0V 8 4 0 0 1 2 3 2.5 2.0 VGS = 3.5V 1.5 VGS = 4.5V 1.0 VGS = 10V 0.5 0 4 4 1.6 20 rDS(on), DRAIN TO 1.0 0.8 -50 TJ = 25oC 15 4 6 8 10 Figure 4.
PAGE 5
VGS, GATE TO SOURCE VOLTAGE(V) 10 3000 ID = 8.6A Ciss CAPACITANCE (pF) 8 VDD = 15V VDD = 10V 6 VDD = 20V 4 2 1000 Coss Crss 100 50 0.1 0 0 4 8 12 16 20 Qg, GATE CHARGE(nC) Figure 7. Gate Charge Characteristics -3 10 TJ = 25oC TJ = VDS = 0V Ig, GATE LEAKAGE CURRENT(A) IAS, AVALANCHE CURRENT(A) 10 125oC -4 10 TJ = 125oC -5 10 TJ = 25oC -6 10 -7 1 0.01 0.1 1 10 tAV, TIME IN AVALANCHE(ms) 10 100 0 5 10 15 20 25 30 VGS, GATE TO SOURCE VOLTAGE(V) Figure 9.
PAGE 6
FDS8858CZ Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted 300 P(PK), PEAK TRANSIENT POWER (W) VGS = 10V FOR TEMPERATURES ABOVE 25oC DERATE PEAK 100 CURRENT AS FOLLOWS: 150 – T A -----------------------125 I = I25 TA = 25oC 10 SINGLE PULSE 1 o RθJA = 135 C/W 0.5 -3 10 -2 -1 10 0 10 1 10 2 10 3 10 10 t, PULSE WIDTH (s) Figure 13. Single Pulse Maximum Power Dissipation 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.
PAGE 7
20 4.0 -ID, DRAIN CURRENT (A) VGS = -10V 16 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX VGS = -5V VGS = -4.5V 12 VGS = -4V VGS = -3.5V 8 4 VGS = -3V 0 0 1 2 3 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 3.5 VGS = -3.5V 3.0 2.5 VGS = -4V 2.0 1.5 VGS = -5V 1.0 VGS = -10V 0.5 4 0 4 8 Figure 15. On- Region Characteristics 16 20 Figure 16. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 60 ID = -7.
PAGE 8
-VGS, GATE TO SOURCE VOLTAGE(V) 10 4000 ID = -7.3A Ciss VDD = -10V 8 CAPACITANCE (pF) VDD = -15V 6 VDD = -20V 4 2 1000 Coss Crss f = 1MHz VGS = 0V 0 0 7 14 21 28 100 0.1 35 1 Figure 22. Capacitance vs Drain to Source Voltage Figure 21.
PAGE 9
300 P(PK), PEAK TRANSIENT POWER (W) VGS = 10V FOR TEMPERATURES ABOVE 25oC DERATE PEAK 100 CURRENT AS FOLLOWS: 150 – T A -----------------------125 I = I25 TA = 25oC 10 SINGLE PULSE 1 o RθJA = 135 C/W 0.5 -3 10 -2 -1 10 0 10 10 1 2 10 3 10 10 t, PULSE WIDTH (s) Figure 27. Single Pulse Maximum Power Dissipation 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.
PAGE 10
tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.