FDS8896 N-Channel PowerTrench® MOSFET tm 30V, 15A, 6.0mΩ Features General Description rDS(on) = 6.0mΩ, VGS = 10V, ID = 15A This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on) and fast switching speed. rDS(on) = 7.3mΩ, VGS = 4.
Symbol VDSS Drain to Source Voltage Parameter Ratings 30 Units V VGS Gate to Source Voltage ±20 V 15 A Continuous (TA = 25 C, VGS = 4.5V, RθJA = 50 C/W) 14 A Pulsed 110 A Single Pulse Avalanche Energy (Note 1) 196 mJ Power dissipation 2.
tON Turn-On Time - - 68 ns td(ON) Turn-On Delay Time - 8 - ns tr Rise Time - 37 - ns td(OFF) Turn-Off Delay Time - 60 - ns tf Fall Time - 24 - ns tOFF Turn-Off Time - - 126 ns ISD = 15A - - 1.25 V ISD = 2.1A - - 1.0 V VDD = 15V, ID = 14A VGS = 10V, RGS = 6.
20 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 15 VGS = 10V VGS = 4.5V 10 5 0.2 RθJA=50oC/W 0 0 0 25 50 75 125 100 150 25 50 TA , AMBIENT TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150 Figure 2. Maximum Continuous Drain Current vs Ambient Temperature DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE o 0.
0 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX 40 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 100 STARTING TJ = 150oC VDS = 5V 30 20 TJ = 25oC TJ = 150oC 10 TJ = -55oC 0 1.5 1 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 Figure 5.
1.10 5000 CISS = CGS + CGD COSS ≅ CDS + CGD 1.05 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA 1.00 0.95 1000 CRSS = CGD VGS = 0V, f = 1MHz 0.90 -80 -40 0 40 80 120 100 0.1 160 TJ , JUNCTION TEMPERATURE (oC) Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature Figure 12.
BVDSS VDS tP VDS L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VDD + RG VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS VGS L VGS = 10V Qg(5) VGS + - Qgs2 VDD DUT VGS = 5V VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18.
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
rev February 2004 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD DRAIN 2 5 10 Ebreak 11 7 17 18 33.
REV February 2004 template FDS8896 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=4e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-12,xti=2.2) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=9e-10,isl=10e-30,nl=10,m=0.39) m..model mmedmod = (type=_n,vto=1.98,kp=10,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.4,kp=350,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.63,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..
JUNCTION th REV February 2004 FDS8896T Copper Area =1.0 in2 CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3 RTHERM1 CTHERM1 8 RTHERM2 RTHERM1 TH 8 1e-1 RTHERM2 8 7 5e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25 RTHERM3 SABER Thermal Model RTHERM4 CTHERM2 7 CTHERM3 6 2 Copper Area = 1.0 in template thermal_model th tl thermal_c th, tl { ctherm.
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