Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFDS8960C, MOSFET

November 2005

FDS8960C Rev C1(W)

www.fairchildsemi.com

FDS8960C

Dual N & P-Channel PowerTrench

MOSFET

General Description

These dual N- and P-Channel enhancement mode

power field effect transistors are produced using

Fairchild Semiconductor’s advanced PowerTrench

process that has been especially tailored to minimize

on-state ressitance and yet maintain superior switching

performance.

These devices are well suited for low voltage and

battery powered applications where low in-line power

loss and fast switching are required.

Features

• Q1: N-Channel

7.0A, 35V R

DS(on)

= 0.024Ω @ V

= 10V

DS(on)

= 0.032Ω @ V

= 4.5V

• Q2: P-Channel

–5A, –35V R

DS(on)

= 0.053Ω @ V

= –10V

DS(on)

= 0.087Ω @ V

= –4.5V

• Fast switching speed

• RoHS compliant

SO-8

Pin 1

SO-8

Absolute Maximum Ratings T

= 25°C unless otherwise noted

Symbol Parameter Q1 Q2 Units

DSS

Drain-Source Voltage 35 –35 V

DS(Avalanche)

Drain-Source Avalanche Voltage (maximum) (Note 3) 40 –40 V

GSS

Gate-Source Voltage

±20 ±25

Drain Current - Continuous (Note 1a) 7 –5 A

- Pulsed 20 –20

Power Dissipation for Dual Operation 2 W

Power Dissipation for Single Operation (Note 1a) 1.6

(Note 1b)

(Note 1c)

0.9

, T

STG

Operating and Storage Junction Temperature Range –55 to +150

°C

Thermal Characteristics

θJA

Thermal Resistance, Junction-to-Ambient (Note 1a) 78

°C/W

θJC

Thermal Resistance, Junction-to-Case (Note 1) 40

°C/W

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity

FDS8960C FDS8960C 13” 12mm 2500 units

S8960C

l N

P-

l P

rTr

FET

Summary of content (8 pages)

PAGE 1
FDS8960C Dual N & P-Channel PowerTrench® MOSFET General Description Features These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state ressitance and yet maintain superior switching performance. • Q1: • Q2: P-Channel –5A, –35V RDS(on) = 0.053Ω @ VGS = –10V RDS(on) = 0.087Ω @ VGS = –4.
PAGE 2
Symbol TA = 25°C unless otherwise noted Parameter Test Conditions Type Min Typ Max Units Q1 24.5 mJ Q2 Q1 Q2 12.
PAGE 3
Symbol Parameter Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd (continued) TA = 25°C unless otherwise noted Test Conditions Type Min Typ Max Units (Note 2) Gate-Drain Charge Q1 VDD = 15 V, ID = 1 A, VGS = 10V, RGEN = 6 Ω Q2 VDD = –15 V, ID = -1 A, VGS = –10V, RGEN = 6 Ω Q1 VDS = 15 V, ID = 7 A, VGS = 5 V Q2 VDS = –15 V, ID = –5 A,VGS = –5 V Q1 Q2 Q1 Q2 Q1 Q2 Q1
PAGE 4
2.6 20 6.0V 4.5V 3.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 10V ID, DRAIN CURRENT (A) 16 12 8 3.0V 4 0 0.5 1 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 2 VGS = 3.5V 1.8 1.6 4.0V 1.4 4.5V 5.0V 1.2 6.0V 10V 1 2 0 Figure 1. On-Region Characteristics. 8 12 ID, DRAIN CURRENT (A) 16 20 0.065 ID = 7A VGS = 10V ID = 3.5A RDS(ON), ON-RESISTANCE (OHM) 1.6 4 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.
PAGE 5
800 10 VGS, GATE-SOURCE VOLTAGE (V) ID = 7A VDS = 10V 15V f = 1 MHz VGS = 0 V 700 8 Ciss 600 CAPACITANCE (pF) 20V 6 4 500 400 300 Coss 200 2 100 0 0 2 4 6 8 10 Crss 0 12 0 5 Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics. 35 50 P(pk), PEAK TRANSIENT POWER (W) RDS(ON) LIMIT 100μs ID, DRAIN CURRENT (A) 30 Figure 8. Capacitance Characteristics. 100 10 1ms 10ms 100ms 1 1s 10s DC VGS = 10V SINGLE PULSE RθJA = 135oC/W 0.1 TA = 25oC 0.
PAGE 6
3.4 20 VGS = -10V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE -6.0V -ID, DRAIN CURRENT (A) -4.5V 16 12 8 -3.5V 4 -3.0V 3.2 3 VGS = - 3.5V 2.8 2.6 2.4 2.2 -4.0V 2 1.8 -4.5V -5.0V 1.6 -6.0V 1.4 1.2 -10V 1 0 0.8 0 0.5 1 1.5 2 2.5 3 3.5 4 0 5 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 13. On-Region Characteristics. 20 0.2 ID = -2.5A ID = -5A VGS = - 10V 1.5 RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 15 Figure 14.
PAGE 7
800 10 -VGS, GATE-SOURCE VOLTAGE (V) ID = -5A VDS = -10V f = 1 MHz VGS = 0 V 700 -15V CISS CAPACITANCE (pF) 8 -20V 6 4 2 600 500 400 300 COSS 200 100 CRSS 0 0 0 2 4 6 8 10 12 0 5 10 Qg, GATE CHARGE (nC) Figure 19. Gate Charge Characteristics. 25 30 35 50 P(pk), PEAK TRANSIENT POWER (W) 100μs RDS(ON) LIMIT 10 1ms 10ms 100ms 1s 10s 1 DC VGS = -10V SINGLE PULSE RθJA = 135oC/W 0.1 TA = 25oC 0.01 0.1 1 10 SINGLE PULSE RθJA = 135°C/W TA = 25°C 40 30 20 10 0 0.
PAGE 8
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 RθJA(t) = r(t) * RθJA 0.2 0.1 o RθJA = 135 C/W 0.1 0.05 P(pk) 0.02 0.01 t1 0.01 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 25. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1c. FDS8960C Rev C1(W) www.fairchildsemi.