Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLinear ICsLinear IC - Video editing Video switcher SSOP 28

April 2007

FMS6501 Rev. 1.0.4

FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

FMS6501

12 Input / 9 Output Video Switch Matrix with Input Clamp,

Input Bias Circuitry, and Output Drivers

Features

■ 12 x 9 Crosspoint Matrix

■ Supports SD, PS, and HD 1080i/1080p Video

■ Input Clamp / Bias Circuitry

■ AC or DC-Coupled Inputs

■ AC or DC-Coupled Outputs

■ Dual-Load (75Ω) Output Drivers with High-Impedance

Disable

■ One-to-One or One-to-Many Input to Output Switching

■ Programmable Gain: +6, +7, +8, or +9dB

■ I

Compatible Digital Interface, Standard Mode

■ 3.3V or 5V Single-Supply Operation

■ Lead-Free SSOP-28 Package

Applications

■ Cable and Satellite Set-Top Boxes

■ TV and HDTV Sets

■ A/V Switchers

■ Personal Video Recorders (PVR)

■ Security / Surveillance

■ Video Distribution

■ Automotive (In-Cabin Entertainment)

Description

The FMS6501 switch matrix provides flexible options for

today’s video applications. The 12 inputs that can be

routed to any of nine outputs. Each input can be routed

to one or more outputs, but only one input may be routed

to any one output. The input to output routing is con-

trolled via an I

C™-compatible digital interface.

Each input supports an integrated clamp option to set the

output sync tip level of video with sync to ~300mV. Alter-

natively, the input may be internally biased to center sig-

nals without sync (Chroma, Pb, Pr) at ~1.25V. These DC

output levels are for the 6dB gain setting. Higher gain

settings increase the DC output levels accordingly. The

input clamp / bias mode is selected via I

Unused outputs may be powered down to reduce power

dissipation.

Ordering Information

Part Number Pb-Free Temperature Range Package Container Quantity

FMS6501MSA28 Yes -40°C to 85°C SSOP-28 Rail 47

FMS6501MSA28X Yes -40°C to 85°C SSOP-28 Reel 2000

Summary of content (14 pages)

PAGE 1
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Features Description ■ 12 x 9 Crosspoint Matrix The FMS6501 switch matrix provides flexible options for today’s video applications. The 12 inputs that can be routed to any of nine outputs. Each input can be routed to one or more outputs, but only one input may be routed to any one output. The input to output routing is controlled via an I2C™-compatible digital interface.
PAGE 2
IN1 C/B IN2 C/B IN12 C/B SDA SCL ADDR Programmable Gain 6, 7, 8, or 9dB VCC (2) GND (2) OUT1 OUT2 OUT9 Programmable Enable/Disable Figure 1. FMS6501 Block Diagram © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.
PAGE 3
IN1 1 28 OUT1 IN2 2 27 OUT2 IN3 3 26 OUT3 IN4 4 25 OUT4 FAIRCHILD Pin# Name Type Description 1 IN1 Input Input, channel 1 2 IN2 Input Input, channel 2 3 IN3 Input Input, channel 3 4 IN4 Input Input, channel 4 5 IN5 Input Input, channel 5 6 IN6 Input Input, channel 6 24 OUT5 23 OUT6 7 VCC Input Positive power supply 7 22 VCCO 8 GND Input Must be tied to ground GND 8 21 GNDO 9 IN7 Input Input, channel 7 IN7 9 20 OUT7 10 IN8 Input Input
PAGE 4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter Min. Max. Unit DC Supply Voltage -0.3 6.0 V Analog and Digital I/O -0.3 Vcc + 0.
PAGE 5
The I2C-compatible interface is used to program output enables, input to output routing, input clamp / bias, and output gain. The I2C address of the FMS6501 is 0x06 (0000 0110) with the ability to offset it to 0x86 (1000 0110) by tying the ADDR pin high. same input channel for one-to-many routing. When the outputs are disabled, they are placed in a high-impedance state. This allows multiple FMS6501 devices to be paralleled to create a larger switch matrix. Typical output power-up time is less than 500ns.
PAGE 6
TA = 25°C, Vcc = 5V, VIN = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with 0.1µF, unused inputs AC-terminated through 75Ω to GND, all outputs AC coupled with 220µF into 150Ω loads, referenced to 400kHz, unless otherwise noted. Symbol ICC Parameter Conditions Supply Current1 Min. No load, all outputs enabled VOUT Video Output Range ROFF Off Channel Output Impedance Output disabled 1 Typ. Max Units 80 100 mA 2.8 Vpp 3.
PAGE 7
TA = 25°C and VCC = 5V unless otherwise noted. Symbol Vil Vih Conditions Min. (1) Parameter SDA, SCL, ADDR (1) SDA, SCL, ADDR Digital Input Low Digital Input High Typ. Max Units 0 1.5 V 3.0 Vcc V fscl Clock Frequency SCK 100 kHz tr Input Rise Time 1.5V to 3V 1000 ns tf Input Fall Time 1.5V to 3V 300 ns 4.7 µs tlow Clock Low Period thigh Clock High Period 4.
PAGE 8
Operation Bit Transfer The I2C-compatible interface conforms to the I2C specification for Standard Mode. Individual addresses may be written. There is no read capability. The interface consists of two lines. These is a serial data line (SDA) and a serial clock line (SCL), both of which must be connected to a positive supply through an external resistor. Data transfer may be initiated only when the bus is not busy. One data bit is transferred during each clock pulse.
PAGE 9
The data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a high-level signal put on the bus by the transmitter, during which the master generates an extra acknowledge-related clock pulse. A slave receiver must generate an acknowledge after the reception of each byte.
PAGE 10
Input Clamp / Bias Circuitry Figure 9 shows the bias mode input circuit and internally controlled voltage at the input pin for AC-coupled inputs. The FMS6501 accommodates AC- or DC-coupled inputs. Lowest voltage set to 625mV Internal clamping and bias circuitry are provided to support AC-coupled inputs. These are selectable through the CLMP bits via the I2C compatible interface. Video source must be AC-coupled For DC-coupled inputs, the device should be programmed to use the 'bias' input configuration.
PAGE 11
For input crosstalk, the switch is open. All inputs are in bias mode. Channel 1 input is driven with a 1Vpp signal, while all other inputs are AC terminated with 75Ω. All outputs are enabled and crosstalk is measured from IN1 to any output. Each of the outputs can be independently powered down and placed in a high-impedance state with the ENABLE bit. This function can be used to mute video signals, to parallel multiple FMS6501 outputs, or to save power.
PAGE 12
FMS6501 Video Switch Matrix Applications General layout and supply bypassing play major roles in high-frequency performance and thermal characteristics. Fairchild offers a demonstration board, FMS6501DEMO, to use as a guide for layout and to aid in device testing and characterization. The FMS6501DEMO is a 4-layer board with a full power and ground plane. For optimum results, follow the steps below as a basis for high frequency layout.
PAGE 13
FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Physical Dimensions Dimensions are in millimeters unless otherwise noted. SSOP-28 Figure 15. FMS6501 28-Lead Small Scale Outline Package (SSOP) © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.
PAGE 14
FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers 14 www.fairchildsemi.com © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.