Datasheet

©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD0721, FOD0720, FOD0710 Rev. 1.0.9 11
FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler
Figure 16. Test Circuit for Propogation Delay Time and Rise Time, Fall Time
Figure 17. Test Circuit for Instantaneous Common Mode Rejection Voltage
V
IN
t
PLH
t
R
V
OUT
V
OL
50%
90%
10%
Input
Output
5V
2.5V
V
OH
t
F
t
PHL
1
2
V
DD2
= 5V
V
O
0.1µF
0V–5V
C
L
3
4
8
7
6
5
0.1µF
V
DD1
= 5V
Pulse width = 40ns
Duty Cycle = 50%
1
2
V
DD2
= 5V
V
O
V
CM
+–
0.1µF
SW
B
A
C
L
3
4
8
7
6
5
0.1µF
V
DD1
= 5V
V
OH
0.8 x V
DD
Switching Pos. (A) V
IN
= 5V
Switching Pos. (B) V
IN
= 0V
GND
1kV
V
OL
V
CM
CM
H
CM
L
0.8V