Datasheet

©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 6
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Typical Performance Curves (Continued)
22
24
26
28
30
32
34
15 20 25 30 35 40 45 50 55
t
P
-Propagation Delay (ns)
C
L
-Output Load Capacitance (pF)
t
PHL
t
PLH
Frequency = 12.5MHz
Duty Cycle = 50%
V
DD1
=V
DD2
=3.3V
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
15 20 25 30 35 40 45 50 55
PWD - Pulse Width Dist ortion (ns)
C
L
-Output Load Capacitance (pF)
Frequency = 12.5MHz
Dut y Cycle = 50%
V
DD1
=V
DD2
=3.3V
4
5
6
7
8
9
10
11
12
15 20 25 30 35 40 45 50 55
t
r
-RiseTime(ns)
C
L
-Output Load Capacitance (pF)
Frequency = 12.5MHz
Dut y Cycl e = 50%
V
DD1
=V
DD2
=3.3V
2
4
6
8
10
12
14
16
15 20 25 30 35 40 45 50 55
t
f
-FallTime(ns)
C
L
-Output Load Capacitance (pF)
Frequency = 12. 5MHz
Duty Cycle = 50%
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0 2000 4000 6000 8000 10000 12000
I
DD1
-Input Supply Current (mA)
f-Frequency (kHz)
T
A
=105°C
T
A
=25°C
T
A
=-40°C
V
DD1
=5.5V
5.0
5.2
5.4
5.6
5.8
6.0
02000 4000 6000 8000 10000 12000
I
DD2
-Output Supply Current (mA)
f-Frequency (kHz)
V
DD 1
=V
DD2
=5.5V
*Pin6Floating
T
A
=105°C
T
A
=25°C
T
A
=-40°C
Figure 7. Typical Propogation Delay vs. Output Load Capacitance
Figure 8. Typical Width Distortion vs. Output Load Capacitance
Figure 9. Typical Rise Time vs. Output Load Capacitance
Figure 10. Typical Fall Time vs. Output Load Capacitance
Figure 11. Input Supply Current vs. Frequency
Figure 12. Output Supply Current vs. Frequency
V
DD1
=V
DD2
=3.3V