Datasheet

©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 7
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Test Circuits
Figure 13. Test Circuit for Propogation Delay Time and Rise Time, Fall Time
Figure 14. Test Circuit for Instantaneous Common Mode Rejection Voltage
V
IN
t
PLH
t
R
V
OUT
V
OL
50%
90%
10%
Input
Output
3.3V
50%
V
OH
t
F
t
PHL
1
2
V
DD2
= 3.3V
V
O
0.1µF
0V–3.3V
C
L
3
4
8
7
6
5
0.1µF
V
DD1
= 3.3V
Pulse width = 40ns
Duty Cycle = 50%
1
2
V
DD2
= 3.3V
V
O
V
CM
+–
0.1µF
SW
B
A
C
L
3
4
8
7
6
5
0.1µF
V
DD1
= 3.3V
V
OH
0.8 x V
DD
Switching Pos. (A) V
IN
= 3.3V
Switching Pos. (B) V
IN
= 0V
GND
1kV
V
OL
V
CM
CM
H
CM
L
0.8V