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FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin

FOD8160 Rev. 1.0.2

July 2014

FOD8160

High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate

Optocoupler in Wide-Body SOP 5-Pin

Features

■

Optoplanar

Packaging Technology Allows More

Than 10 mm Creepage and Clearance Distance, and

0.5 mm Insulation Distance to Achieve Reliable and

High Voltage Insulation

■

High Noise Immunity Characterized by Common

Mode Transient Immunity (CMTI)

– 20 kV/µs Minimum CMTI

■

Specifications Guaranteed Over 3 V to 5.5 V Supply

Voltage and -40°C to 100°C Extended Industrial

Temperature Range

■

High-Speed, 10 Mbit/s Data Rate (NRZ)

■

Safety and Regulatory Approvals

– UL1577, 5,000 VAC

RMS

for 1 Minute

– DIN-EN/IEC60747-5-5, 1,414 V Peak Working

Insulation Voltage

Applications

■

Isolating Intelligent Power Module

■

Isolating Industrial Communication Interface

Related Resources

■

www.fairchildsemi.com/products/opto/

■

www.fairchildsemi.com/pf/FO/FODM8061.html

■

www.fairchildsemi.com/pf/FO/FODM611.html

Description

The FOD8160 is a 3.3 V / 5 V high-speed logic gate

optocoupler with open-collector output, which supports

isolated communications to allow digital signals to

communicate between systems without conducting

ground loops or hazardous voltages. The device utilizes

Fairchild’s prioprietary Optoplanar

coplanar packaging

technology and optimized IC design to achieve high-

noise immunity, characterized by high common-mode

rejection specifications.

The FOD8160, packaged in a wide-body SOP 5-Pin

package, consists of an aluminium gallium arsenide

(AlGaAs) LED and an integrated high-speed

photodetector. The output of the detector IC is an open

collector Schottky-clamped transistor. The electrical and

switching characteristics are guaranteed over the

extended industrial temperature range of -40°C to 100°C

and a V

range of 3 V to 5.5 V.

Functional Schematic

Figure 1. Functional Schematic

ANODE

CATHODE GND

Summary of content (14 pages)

PAGE 1
FOD8160 High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Features Description ■ Optoplanar® The FOD8160 is a 3.3 V / 5 V high-speed logic gate optocoupler with open-collector output, which supports isolated communications to allow digital signals to communicate between systems without conducting ground loops or hazardous voltages.
PAGE 2
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Truth Table LED Output Off HIGH On LOW Pin Configuration 1 6 ANODE CATHODE VCC 5 3 VO 4 GND Figure 2. Pin Configuration Pin Definitions Pin # Name Description 1 Anode 3 Cathode 4 GND Output Ground 5 VO Output Voltage 6 VCC Output Supply Voltage ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.2 Anode Cathode www.fairchildsemi.
PAGE 3
As per DIN EN/IEC60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit data below. Compliance with the safety ratings shall be ensured by means of protective circuits. Symbol Parameter Min. Typ. Max. Unit Installation Classifications per DIN VDE 0110/1.
PAGE 4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified.
PAGE 5
Apply over all recommended conditions, typical value is measured at TA = 25°C. Symbol Parameter Conditions Min. 5,000 VISO Input-Output Isolation Voltage TA = 25°C, R.H. < 50%, t = 1.0 min, II-O ≤ 20 µA(3)(4) RISO Isolation Resistance VI-O = 500 V(3) CISO Isolation Capacitance VI-O = 0 V, frequency = 1.0 MHz(3) Typ. Max. Units VACRMS 1011 Ω 1.0 pF Notes: 3. Device is considered a two-terminal device: pins 1 and 3 are shorted together and pins 4, 5, and 6 are shorted together. 4.
PAGE 6
Apply over all recommended conditions; TA = -40°C to +100°C, VCC = 3.3 V, IF = 6.0 mA; unless otherwise specified. Typical value is measured at TA = 25°C and VCC = 3.3 V. Symbol Parameter Conditions Min. Typ. RL = 350 Ω Data Rate Max.
PAGE 7
©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.2 www.fairchildsemi.com 7 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Notes: 5. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH between any two units from the same manufacturing date code that are operated at same case temperature (±5°C), at same operating conditions, with equal loads (RL = 350 Ω, CL = 15 pF), and with an input rise time less than 5 ns. 6.
PAGE 8
IFHL – THRESHOLD INPUT CURENT (mA) IF – INPUT LED CURENT (mA) 100 10 1 0.1 0.001 0.6 0.8 -40°C 25°C TA = 100°C 0.01 1.0 1.2 1.4 1.6 1.8 3.0 IOL = 13 mA 2.5 VCC = 3.3 V VCC = 5.0 V 2.0 1.5 1.0 -40 2.0 -20 VOL – LOGIC LOW OUTPUT VOLTAGE (V) 0.50 IOL = 13 mA IF = 6 mA 0.45 0.40 VCC = 3.3 V 0.35 VCC = 5.0 V 0.30 0.25 -20 0 20 40 60 80 100 ICCH – LOGIC HIGH OUTPUT SUPPLY CURRENT (mA) ICCL – LOGIC LOW OUTPUT SUPPLY CURRENT (mA) 8 VCC = 5.0 V 6 VCC = 3.
PAGE 9
80 IF = 0 mA (for ICCH), 10 mA (for ICCL) TA = 25°C tP – PROPAGATION DELAY (ns) ICC – OUTPUT SUPPLY CURRENT (mA) 10 8 ICCL 6 ICCH 4 2 0 3.0 3.5 4.0 4.5 5.0 Frequency = 5 MHz, 50% Duty Cycle IF = 6 mA, RL = 350 Ω 70 60 tPLH @ VCC = 3.3 V 50 tPLH @ VCC = 5.0 V 40 tPHL @ VCC = 5.0 V 20 -40 5.5 -20 VCC – OUTPUT SUPPLY VOLTAGE (V) (|tPHL – tPLH|) – PULSE WIDTH DISTORTION (ns) tP – PROPAGATION DELAY (ns) Frequency = 5 MHz, 50% Duty Cycle RL = 350 Ω, TA = 25°C 60 tPLH @ VCC = 3.
PAGE 10
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Test Circuit Pulse Gen. 5 MHz tf = tr = 5 ns DC = 50% IF 0.1 μF Bypass 350 Ω CL Input Monitoring Mode VO Monitoring Node RM (IF = 6 mA) Input 50% tf tr 90% 1.5 V 10% VOL Output tPHL tPLH Figure 15. Test Circuit for Propagation Delay, Rise Time, and Fall Time IF VCC 0.1 μF Bypass SW 350 Ω CL VO Monitoring Node RM VCM Pulse Gen 1 kV VCM 90% 10% 0V tr tf VOH VO (IF = 0 mA) 2V 0.
PAGE 11
Part Number Package Packing Method FOD8160 Wide Body SOP 5-Pin Tube (100 units per tube) FOD8160R2 Wide Body SOP 5-Pin Tape and Reel (1,000 units per reel) FOD8160V Wide Body SOP 5-Pin, DIN EN/IEC60747-5-5 Option Tube (100 units per tube) FOD8160R2V Wide Body SOP 5-Pin, DIN EN/ IEC60747-5-5 Option Tape and Reel (1,000 units per reel) All packages are lead free per JEDEC: J-STD-020B standard.
PAGE 12
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Reflow Profile Temperature (°C) TP 260 240 TL 220 200 180 160 140 120 100 80 60 40 20 0 Max. Ramp-up Rate = 3°C/s Max. Ramp-down Rate = 6°C/s tP Tsmax tL Preheat Area Tsmin ts 120 240 360 Time 25°C to Peak Time (seconds) Figure 17.
PAGE 13
0.20 C A-B 3.95 0.60 2X 1.27 4 6 D 1.38 A 6 4 1.27 4.60 11.38 11.80 11.60 9.20 0.10 C D 2X 1 3 1 0.33 C PIN ONE INDICATOR B 2.54 0.25 5X 0.51 0.31 2.54 C A-B D LAND PATTERN RECOMMENDATION 5 TIPS A 2.65 2.45 0.10 C 3 SEATING PLANE 2.95 MAX 0.10 C 0.30 0.10 5X C NOTES: UNLESS OTHERWISE SPECIFIED 1.35 1.15 GAUGE PLANE 8° 0° 0.25 C (R1.29) SEATING PLANE SCALE: 3.2:1 0.74 0.44 A) THIS PACKAGE DOES NOT CONFORM TO ANY STANDARD. B) ALL DIMENSIONS ARE IN (R0.54) MILLIMETERS.
PAGE 14
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