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FQA13N80_F109 RevC1 20131102

FQA13N80_F109

N-Channel QFET

MOSFET

800 V, 12.6 A, 750 mΩ

Description

FQA13N80_F109 — N-Channel QFET

MOSFET

FQA13N80_F109 Rev.

www.fairchildsemi.com

This N-Channel enhancement mode power MOSFET is

produced using Fairchild Semiconductor’s proprietary

planar stripe and DMOS technology. This advanced

MOSFET technology has been especially tailored to

reduce on-state resistance, and to provide superior

switching performance and high avalanche energy

strength. These devices are suitable for switched mode

power supplies, active power factor

correction (PFC), and

electronic lamp ballasts.

Features

Absolute Maximum Ratings T

= 25

C unless otherwise noted.

TO-3PN

•

12.6 A, 800 V, R

DS(on)

= 750 mΩ (Max.) @ V

= 10 V,

= 6.3 A

•

Low Gate Charge (Typ. 68 nC)

•

Low Crss (Ty

p. 30 pF)

•

100% Avalanche Tested

Thermal Characteristics

Symbol Parameter FQA13N80_F109

Unit

DSS

Drain-Source Voltage 800 V

Drain Current 12.6 A- Continuous (T

= 25°C)

- Continuous (T

= 100°C) 8.0 A

Drain Current - Pulsed

(Note 1)

50.4 A

GSS

Gate-Source Voltage ± 30 V

Single Pulsed Avalanche Energy

(Note 2)

1100 mJ

Avalanche Current

(Note 1)

12.6 A

Repetitive Avalanche Energy

(Note 1)

30 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

4.0 V/ns

Power Dissipation (T

= 25°C) 300 W

- Derate above 25°C 2.38 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds

300 °C

Symbol Parameter

FQA13N80_F109

nit

θJC

Thermal Resistance, Junction-to-Case, Max.

0.42

°C/W

θCS

Thermal Resistance, Case-to-Sink, Typ.

0.24

°C/W

θJA

Thermal Resistance, Junction-to-Ambient, Max.

°C/W

April 2014

Summary of content (8 pages)

PAGE 1
FQA13N80_F109 N-Channel QFET® MOSFET 800 V, 12.6 A, 750 mΩ Description Features This N-Channel enhancement mode power MOSFET is produced using Fairchild Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength.
PAGE 2
Part Number FQA13N80_F109 Package TO-3PN Top Mark FQA13N80 Electrical Characteristics T Symbol Packing Method Tube Reel Size N/A Tape Width N/A Quantity 30 units o C = 25 C unless otherwise noted. Parameter Test Conditions Min Typ Max Unit 800 -- -- V -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C -- 0.
PAGE 3
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V Top : ID, Drain Current [A] 1 10 ID, Drain Current [A] 1 10 0 10 o 150 C o 25 C 0 10 o -55 C ※ Notes : 1. 250µs Pulse Test 2. TC = 25℃ ※ Notes : 1. VDS = 50V 2. 250µs Pulse Test -1 -1 10 -1 0 10 10 1 10 2 10 4 6 8 10 VGS, Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 3. On-Resistance Variation vs.
PAGE 4
Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 3.0 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 µA 0.9 0.8 -100 -50 0 50 100 150 2.5 RDS(ON), (Normalized) Drain-Source On-Resistance BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 6.3 A 0.5 0.0 -100 200 -50 o 0 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 10.
PAGE 5
FQA13N80_F109 — N-Channel QFET® MOSFET 50KΩ 200nF 12V VGS Same Type as DUT Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on t off tf Figure 13. Resistive Switching Test Circuit & Waveforms VDS BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L BVDSS IAS ID RG V 10V GS GS VDD ID (t) VDS (t) VDD DUT tp Time tp Figure 14.
PAGE 6
+ VDS _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms ©2007 Fairchild Semiconductor Corporation FQA13N80_F109 Rev. C2 6 www.
PAGE 7
FQA13N80_F109 — N-Channel QFET® MOSFET Mechanical Dimensions Figure 16. TO3PN, 3-Lead, Plastic, EIAJ SC-65 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.