Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQB1P50TM, MOSFET

October 2013

www.fairchildsemi.com

Thermal Characteristics

Symbol Parameter

FQB1P50TM

Unit

JC

Thermal Resistance, Junction to Case, Max

1.98

C/W

JA

Thermal Resistance, Junction to Ambient (minimum pad of 2 oz copper), Max. 62.5

Thermal Resistance, Junction to Ambient (* 1 in

pad of 2 oz copper), Max.

FQB1P50

P-

Channel QFET

MOSFET

-500 V, -1.5 A, 10.5 Ω

Description

This P-Channel enhancement mode power MOSFET is

produced using Fairchild Semiconductor’s proprietary

planar stripe and DMOS technology. This advanced

MOSFET technology has been especially tailored to

reduce on-state resistance, and to provide superior

switching performance and high avalanche energy

strength.

These devices are suitable for switched mode

power supplies, active power factor correction (PFC), and

electronic lamp ballasts.

Features

•

-1.5 A, -500 V, R

DS(on)

= 10.5 Ω (Max.) @ V

= -10 V,

= -0.75 A

•

Low Gate Charge (Typ. 11 nC)

•

Low Crss (Typ. 6.0 pF)

•

100% Avalanche Tested

Absolute Maximum Ratings T

= 25°C unless otherwise noted

Symbol Parameter

FQB1P50TM

Unit

DSS

Drain-Source Voltage -500 V

Drain Current -1.5 A

- Continuous (T

= 25°C)

- Continuous (T

= 100°C)

-0.95 A

Drain Current - Pulsed

(Note 1)

-6.0 A

GSS

Gate-Source Voltage ± 30 V

Single Pulsed Avalanche Energy

(Note 2)

110 mJ

Avalanche Current

(Note 1)

-1.5 A

Repetitive Avalanche Energy

(Note 1)

6.3 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

-4.5 V/ns

Power Dissipation (T

= 25°C) *

3.13 W

Power Dissipation (T

= 25°C)

63 W

- Derate above 25°C 0.51 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering purposes,

1/8” from case for 5 seconds

300 °C

• RoHS Compliant

FQB1P50 — P-Channel QFET

MOSFET

FQB1P50 Rev. C1

-PAK

Summary of content (8 pages)

PAGE 1
FQB1P50 P-Channel QFET® MOSFET -500 V, -1.5 A, 10.5 Ω Description Features This P-Channel enhancement mode power MOSFET is produced using Fairchild Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength.
PAGE 2
Device Marking Device FQB1P50TM FQB1P50 Elerical Characteristics Symbol Package D2-PAK Reel Size 330mm Tape Width 24mm Quantity 800 TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Unit -500 -- -- V -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage ∆BVDSS / ∆TJ VGS = 0 V, ID = -250 µA Breakdown Voltage Temperature Coefficient ID = -250 µA, Referenced to 25°C -- - IDSS Zero Gate Voltage Drain Current VDS = -500 V, VGS = 0 V -- -- -1 µA
PAGE 3
VGS -15.0 V -10.0 V -8.0 V -7.0 V -6.5 V -6.0 V Bottom : -5.5 V 0 -I D, Drain Current [A] 10 -I D , Drain Current [A] Top : -1 10 ※ Notes : 1. 250μs Pulse Test 2. TC = 25℃ 150℃ 25℃ ※ Notes : 1. VDS = -50V 2. 250μs Pulse Test -55℃ -2 10 0 10 -1 -1 0 10 10 1 10 2 10 4 6 8 10 -VGS , Gate-Source Voltage [V] -VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2.
PAGE 4
(Continued) 2.5 2.0 1.1 RDS(ON) , (Normalized) Drain-Source On-Resistance -BV DSS , (Normalized) Drain-Source Breakdown Voltage 1.2 1.0 ※ Notes : 1. VGS = 0 V 2. ID = -250 μA 0.9 0.8 -100 -50 0 50 100 150 1.5 1.0 ※ Notes : 1. VGS = -10 V 2. ID = -0.75 A 0.5 0.0 -100 200 -50 0 50 100 150 200 o o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 1.
PAGE 5
FQB1P50 — P-Channel QFET® MOSFET Figure 12. Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ 200nF 12V Qg -10V 300nF VDS VGS Qgs Qgd DUT -3mA IG = const. Charge Figure 13. Resistive Switching Test Circuit & Waveforms VDS RG RL t on td(on) VDD VGS VGS t off tr td(off) tf 10% DUT VGS -10V VDS 90% Figure 14.
PAGE 6
+ VDS DUT _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Compliment of DUT (N-Channel) VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop VDD Body Diode Recovery dv/dt ©2000 Fairchild Semiconductor Corporation FQB1P50 Rev. C1 6 www.fairchildsemi.
PAGE 7
FQB1P50 — P-Channel QFET® MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 16. 2LD,TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.