Datasheet

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FQB22P10TM_F085 100V P-Channel MOSFET

FQB22P10TM_F085

100V P-Channel MOSFET

General Description

These P-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for low voltage applications such as audio amplifier,

high efficiency switching DC/DC converters, and DC motor

control.

Features

• -22A, -100V, R

DS(on)

= 0.125Ω

= -10 V

• Low

gate charge ( typical 40 nC

)

• Low Crss ( typical 160 pF)

• Fast s

witching

• 100% avalanche tested

• Improved dv/dt capability

• 175°C maximum junction tem

erature rating

Absolute Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Symbol Parameter FQB22P10TM_F085 Units

DSS

Drain-Source Voltage -100 V

Drain Current

- Continuous (T

= 25°C)

-22 A

- Continuous (T

= 100°C)

-15.6 A

Drain Current - Pulsed

(Note 1)

-88 A

GSS

Gate-Source Voltage ±30 V

Single Pulsed Avalanche Energy

(Note 2)

710 mJ

Avalanche Current

(Note 1)

-22 A

Repetitive Avalanche Energy

(Note 1)

12.5 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

-6.0 V/ns

Power Dissipation (T

= 25°C) *

3.75 W

Power Dissipation (T

= 25°C)

125 W

- Derate above 25°C 0.83 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +175 °C

Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds

300 °C

Symbol Parameter Typ Max Units

θJC

Thermal Resistance, Junction-to-Case -- 1.2 °C/W

θJA

Thermal Resistance, Junction-to-Ambient * -- 40 °C/W

θJA

Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W

* When mounted on the minimum pad size recommended (PCB Mount)

-PAK

FQB Series

• RoHS Compliant

• Qualified to AEC Q101

February 2009

QFET

FQB22P10TM_F085 Rev. A

Summary of content (8 pages)

PAGE 1
QFET ® FQB22P10TM_F085 100V P-Channel MOSFET General Description Features These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode.
PAGE 2
Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units -100 -- -- V -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = -250 µA, Referenced to 25°C -- -0.
PAGE 3
VGS -15.0 V -10.0 V -8.0 V -7.0 V -6.0 V -5.5 V -5.0 V Bottom : -4.5 V 1 10 -ID , Drain Current [A] -ID, Drain Current [A] Top : 1 10 175℃ 25℃ 0 10 -55℃ 0 10 ※ Notes : 1. VDS = -40V 2. 250μ s Pulse Test ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ -1 -1 0 10 10 1 10 10 2 4 -VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics 6 -VGS , Gate-Source Voltage [V] 10 Figure 2. Transfer Characteristics Figure 2. Transfer Characteristics 0.
PAGE 4
(Continued) 2.5 1.2 -BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.0 RDS(ON) , (Normalized) Drain-Source On-Resistance 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = -250 μ A 0.9 0.8 -100 -50 0 50 100 150 1.5 1.0 ※ Notes : 1. VGS = -10 V 2. ID = -11 A 0.5 0.0 -100 200 -50 0 50 100 150 200 o o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
FQB22P10TM_F085 100V P-Channel MOSFET Gate Charge Test Circuit & Waveform 50KΩ 200nF 12V VGS Same Type as DUT Qg -10V 300nF VDS VGS Qgs Qgd DUT -3mA Charge Resistive Switching Test Circuit & Waveforms VDS RG RL t on td(on) VDD VGS VGS t off tr td(off) tf 10% DUT -10V VDS 90% Unclamped Inductive Switching Test Circuit & Waveforms VDS BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L tp ID RG VDD VDD IAS BVDSS tp FQB22P10TM_F085 Rev.
PAGE 6
FQB22P10TM_F085 100V P-Channel MOSFET Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT _ I SD L Driver RG Compliment of DUT (N-Channel) VGS VGS ( Driver ) VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current I SD ( DUT ) IRM di/dt IFM , Body Diode Forward Current VSD VDS ( DUT ) Body Diode Forward Voltage Drop VDD Body Diode Recovery dv/dt FQB22P10TM_F085 Rev. A 6 www.
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4.50 ±0.20 9.90 ±0.20 +0.10 2.00 ±0.10 2.54 TYP (0.75) ° ~3 0° 0.80 ±0.10 1.27 ±0.10 2.54 ±0.30 15.30 ±0.30 0.10 ±0.15 2.40 ±0.20 4.90 ±0.20 1.40 ±0.20 9.20 ±0.20 1.30 –0.05 1.20 ±0.20 (0.40) D2-PAK +0.10 0.50 –0.05 2.54 TYP 9.20 ±0.20 (2XR0.45) 4.90 ±0.20 15.30 ±0.30 10.00 ±0.20 (7.20) (1.75) 10.00 ±0.20 (8.00) (4.40) 0.80 ±0.10 Dimensions in Millimeters FQB22P10TM_F085 Rev. A 7 www.fairchildsemi.
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