Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQB50N06TM, MOSFET

October 2013

FQB50N06 / FQI50N06 — N-Channel QFET

MOSFET

www.fairchildsemi.com

Absolute Maximum Ratings T

= 25°C unless otherwise noted

Symbol Parameter

FQB50N06TM / FQI50N06TU Unit

DSS

Drain-Source Voltage 60 V

Drain Current

- Continuous (T

= 25°C)

50 A

- Continuous (T

= 100°C)

35.4 A

Drain Current - Pulsed

(Note 1)

200 A

GSS

Gate-Source Voltage ± 25 V

Single Pulsed Avalanche Energy

(Note 2)

490 mJ

Avalanche Current

(Note 1)

50 A

Repetitive Avalanche Energy

(Note 1)

12 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

7.0 V/ns

Power Dissipation (T

= 25°C) *

3.75 W

Power Dissipation (T

= 25°C)

120 W

- Derate above 25°C 0.8 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +175 °C

Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds

300 °C

FQB50N06 / FQI50N06

N-Channel QFET

MOSFET

This N-Channel enhancement mode power MOSFET is

produced

using Fairchild Semiconductor’s proprietary planar

stripe and DMOS technology. This advanced MOSFET

technology has been especially tailored to reduce on-state

resistance, and to provide superior switching performance

and high avalanche energy strength. These devices are

suitable for switched mode power supplies, audio amplifier,

DC motor control, and variable switching power applications.

Features

•

50 A , 6

0 V, R

DS(on)

= 22 mΩ (Max.) @V

= 10 V,

25 A

•

Low Gate Charge (Typ. 31 nC)

•

Low Crss (Ty

. 65 pF)

• 100% Avalanche Tested

• 175°C Maximum Junction Temperature Rating

60 V, 50 A, 22 mΩ

Description

-PAK

Thermal Characteristics

Symbol Parameter Unit

JC

Thermal Resistance, Junction to Case, Max.

1.24

C/W

JA

Thermal Resistance, Junction to Ambient (minimum pad of 2 oz copper), Max.

62.5

Thermal Resistance, Junction to Ambient (* 1 in

pad of 2 oz copper), Max.

FQB50N06TM

FQI50N06TU

FQB50N06 / FQI50N06 Rev. C1

Summary of content (9 pages)

PAGE 1
FQB50N06 / FQI50N06 N-Channel QFET® MOSFET 60 V, 50 A, 22 mΩ Description Features This N-Channel enhancement mode power MOSFET is produced using Fairchild Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength.
PAGE 2
Device Marking FQB50N06 Device FQB50N06TM Package D2-PAK Reel Size Tape Width Quantity 330mm 24mm FQI50N06 FQI50N06TU I2-PAK - - 800 50 Electrical Characteristics Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Unit Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 -- -- V ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C -- 0.
PAGE 3
VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V Top : ID, Drain Current [A] 2 10 ID, Drain Current [A] 2 10 1 10 1 10 175℃ 25℃ ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ 0 ※ Notes : 1. VDS = 30V 2. 250μ s Pulse Test -55℃ 10 0 -1 0 10 10 1 10 10 2 4 8 10 VGS, Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.05 2 VGS = 10V 0.
PAGE 4
(Continued) 2.5 2.0 1.1 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 1.2 1.5 1.0 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 0.5 150 ※ Notes : 1. VGS = 10 V 2. ID = 25 A 0.0 -100 200 -50 10 150 Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
FQB50N06 / FQI50N06 — N-Channel QFET® MOSFET Figure 12. Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ 200nF 12V Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 13. Resistive Switching Test Circuit & Waveforms VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on tf t off Figure 14.
PAGE 6
DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2000 Fairchild Semiconductor Corporation FQB50N06 / FQI50N06 Rev. C1 6 www.fairchildsemi.
PAGE 7
FQB50N06 / FQI50N06 — N-Channel QFET® MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 16. 2LD,TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
FQB50N06 / FQI50N06 — N-Channel QFET® MOSFET Mechanical Dimensions TO-262 3L (I2PAK) Figure 17. 3LD, TO262, Jedec Variation AA (12PAK) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 9
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.