Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQB6N80TM, MOSFET

September 2000

Rev. A, September 2000

FQB6N80 / FQI6N80

QFET

FQB6N80 / FQI6N80

800V N-Channel MOSFET

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for high efficiency switch mode power supply.

Features

• 5.8A, 800V, R

DS(on)

= 1.95Ω @V

= 10 V

• Low gate charge ( typical 31 nC)

• Low Crss ( typical 14 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

Absolute Maximum Ratings

= 25°C unless otherwise noted

Thermal Characteristics

Symbol Parameter FQB6N80 / FQI6N80 Units

DSS

Drain-Source Voltage 800 V

Drain Current

- Continuous (T

= 25°C)

5.8 A

- Continuous (T

= 100°C)

3.67 A

Drain Current - Pulsed

(Note 1)

23.2 A

GSS

Gate-Source Voltage ± 30 V

Single Pulsed Avalanche Energy

(Note 2)

680 mJ

Avalanche Current

(Note 1)

5.8 A

Repetitive Avalanche Energy

(Note 1)

15.8 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

4.0 V/ns

Power Dissipation (T

= 25°C) *

3.13 W

Power Dissipation (T

= 25°C)

158 W

- Derate above 25°C 1.27 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds

300 °C

Symbol Parameter Typ Max Units

θJC

Thermal Resistance, Junction-to-Case -- 0.79 °C/W

θJA

Thermal Resistance, Junction-to-Ambient * -- 40 °C/W

θJA

Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W

* When mounted on the minimum pad size recommended (PCB Mount)

-PAK

FQB Series

-PAK

FQI Series

Summary of content (9 pages)

PAGE 1
FQB6N80 / FQI6N80 September 2000 QFET TM FQB6N80 / FQI6N80 800V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode.
PAGE 2
Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 800 -- -- V -- 0.9 -- V/°C VDS = 800 V, VGS = 0 V -- -- 10 µA VDS = 640 V, TC = 125°C -- -- 100 µA Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA 3.0 -- 5.0 V -- 1.5 1.95 Ω -- 5.
PAGE 3
VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V Top : ID, Drain Current [A] 1 10 o 150 C ID, Drain Current [A] 1 10 0 10 o 25 C 0 10 o -55 C ※ Notes : 1. 250μs Pulse Test 2. TC = 25℃ -1 10 ※ Notes : 1. VDS = 50V 2. 250μs Pulse Test -1 -1 0 10 10 1 10 2 10 4 6 8 10 VGS, Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2.
PAGE 4
FQB6N80 / FQI6N80 Typical Characteristics (Continued) 3.0 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μA 0.9 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 2.9 A 0.5 0.0 -100 200 -50 o 0 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs Temperature Figure 8.
PAGE 5
FQB6N80 / FQI6N80 Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL VDS 90% VDD VGS RG VGS DUT 10V 10% td(on) tr td(off) t on tf t off Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG VDD DUT 10V tp ©2000 Fairchild Semiconductor International ID (t) VDS (t) VDD tp T
PAGE 6
FQB6N80 / FQI6N80 Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2000 Fairchild Semiconductor International Rev.
PAGE 7
4.50 ±0.20 9.90 ±0.20 +0.10 2.00 ±0.10 2.54 TYP (0.75) ° ~3 0° 0.80 ±0.10 1.27 ±0.10 2.54 ±0.30 15.30 ±0.30 0.10 ±0.15 2.40 ±0.20 4.90 ±0.20 9.20 ±0.20 1.30 –0.05 1.20 ±0.20 (0.40) D2PAK 1.40 ±0.20 +0.10 0.50 –0.05 2.54 TYP 4.90 ±0.20 (2XR0.45) 9.20 ±0.20 10.00 ±0.20 (7.20) (1.75) 10.00 ±0.20 (8.00) (4.40) 15.30 ±0.30 FQB6N80 / FQI6N80 Package Dimensions 0.80 ±0.10 ©2000 Fairchild Semiconductor International Rev.
PAGE 8
FQB6N80 / FQI6N80 Package Dimensions (Continued) I2PAK 4.50 ±0.20 (0.40) 9.90 ±0.20 +0.10 MAX13.40 9.20 ±0.20 (1.46) 1.20 ±0.20 1.30 –0.05 0.80 ±0.10 2.54 TYP 2.54 TYP 10.08 ±0.20 1.47 ±0.10 MAX 3.00 (0.94) 13.08 ±0.20 ) 5° (4 1.27 ±0.10 +0.10 0.50 –0.05 2.40 ±0.20 10.00 ±0.20 ©2000 Fairchild Semiconductor International Rev.
PAGE 9
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