Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQD12N20LTM, MOSFET

January 2014

Thermal Characteristics

FQD12N20L

N-Channel QFET

MOSFET

200 V, 9.0 A, 280 mΩ

Description

FQD12N20L Rev

. C2

www.fairchildsemi.com

FQD12N20L — N-Channel QFET

MOSFET

This N-Channel enhancement mode power MOSFET is

produced using Fairchild Semiconductor’s proprietary planar

stripe and DMOS technology. This advanced MOSFET

technology has been especially tailored to reduce on-state

resistance, and to provide superior switching performance

and high avalanche energy strength. These devices are

suitable for switched mode power supplies, active power

factor correction (PFC), and electronic lamp ballasts.

Features

•

9.0 A, 200 V, R

DS(on)

= 280 mΩ (Max.) @ V

= 10 V,

= 4.5 A

•

Low Gate Charge (Typ. 16 nC)

•

Low Crss (Typ. 17 pF)

• 100% Avalanche Tested

Absolute Maximum Ratings T

= 25°C unless otherwise noted.

D-PAK

Symbol Parameter

FQD12N20LTM Unit

DSS

Drain-Source Voltage 200 V

Drain Current 9.0 A

- Continuous (T

= 25°C)

- Continuous (T

= 100°C)

5.7 A

Drain Current - Pulsed

(Note 1)

36 A

GSS

Gate-Source Voltage ± 20 V

Single Pulsed Avalanche Energy

(Note 2)

210 mJ

Avalanche Current

(Note 1)

9.0 A

Repetitive Avalanche Energy

(Note 1)

5.5 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

5.5 V/ns

Power Dissipation (T

= 25°C) *

2.5 W

Power Dissipation (T

= 25°C)

55 W

- Derate above 25°C 0.44 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering,

1/8" from case for 5 seconds

300 °C

Symbol Parameter

FQD12N20LTM

Unit

JC

Thermal Resistance, Junction to Case, Max.

2.27

C/W

JA

Thermal Resistance, J

unction to Ambi

ent (

inimum

of 2

oz Copper), Max.

110

Thermal Resistance, Junction to Ambient (*1 in

Pad of 2-oz Copper), Max.

Summary of content (8 pages)

PAGE 1
FQD12N20L N-Channel QFET® MOSFET 200 V, 9.0 A, 280 mΩ Description Features This N-Channel enhancement mode power MOSFET is produced using Fairchild Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength.
PAGE 2
Part Number FQD12N20LTM Electrical Characteristics Symbol Package DPAK Top Mark FQD12N20L Packing Method Tape and Reel Reel Size 330 mm Tape Width 16 mm Quantity 2500 units TC = 25°C unless otherwise noted. Parameter Test Conditions Min. Typ. Max. Unit 200 -- -- V -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C -- 0.
PAGE 3
1 ID, Drain Current [A] ID , Drain Current [A] 10 ※ Notes : 1. 250μs Pulse Test 2. TC = 25℃ -1 10 150℃ 0 25℃ 10 -55℃ ※ Notes : 1. VDS = 30V 2. 250μs Pulse Test -1 -1 0 10 10 1 10 10 0 2 4 6 8 10 VGS, Gate-Source Voltage [V] VDS , Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 1.2 1 VGS = 5 V 0.9 VGS = 10V 0.6 0.3 0.0 0 10 150℃ 25℃ ※ Notes : 1. VGS = 0V 2. 250μs Pulse Test -1 0 6 12 18 24 30 10 36 0.2 0.4 0.
PAGE 4
(Continued) 1.2 3.0 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μA 0.9 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 5.8 A 0.5 0.0 -100 200 -50 0 50 100 150 200 o o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 9.
PAGE 5
200nF 12V FQD12N20L — N-Channel QFET® MOSFET VGS Same Type as DUT 50KΩ Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on tf t off Figure 13. Resistive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG V 10V GS GS VDD ID (t) VDS (t) VDD DUT tp Time tp Figure 14.
PAGE 6
+ VDS _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms ©2009 Fairchild Semiconductor Corporation FQD12N20L Rev. C2 6 www.
PAGE 7
FQD12N20L — N-Channel QFET® MOSFET Mechanical Dimensions Figure 16. TO252 (D-PAK), Molded, 3-Lead, Option AA&AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.