Datasheet

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FQD12P10TM_F085 P-Channel MOSFET

FQD12P10TM_F085

100V P-Channel MOSFET

General Description

These P-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for low voltage applications such as audio amplifier,

high efficiency switching DC/DC converters, and DC motor

control.

Features

• -9.4A, -100V, R

DS(on)

= 0.29Ω @V

= -10 V

• Low gate charge ( typical 21 nC)

• Low Crss ( typical 65 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

Absolute Maximum Ratings

= 25°C unless otherwise noted

Thermal Characteristics

Symbol Parameter

Ratings Units

DSS

Drain-Source Voltage -100 V

Drain Current

- Continuous (T

= 25°C)

-9.4 A

- Continuous (T

= 100°C)

-6.0 A

Drain Current - Pulsed

(Note 1)

-37.6 A

GSS

Gate-Source Voltage ± 30 V

Single Pulsed Avalanche Energy

(Note 2)

370 mJ

Avalanche Current

(Note 1)

-9.4 A

Repetitive Avalanche Energy

(Note 1)

5.0 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

-6.0 V/ns

Power Dissipation (T

= 25°C) *

2.5 W

Power Dissipation (T

= 25°C)

50 W

- Derate above 25°C 0.4 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering purposes,

1/8! from case for 5 seconds

300 °C

Symbol Parameter Typ Max Units

θJC

Thermal Resistance, Junction-to-Case -- 2.5 °C/W

θJA

Thermal Resistance, Junction-to-Ambient * -- 50 °C/W

θJA

Thermal Resistance, Junction-to-Ambient -- 110 °C/W

* When mounted on the minimum pad size recommended (PCB Mount)

D-PAK

FQD12P10TM_F085 Rev. A

www.fairchildsemi.com1

February 2010

•

Qualified to AEC Q101

•

RoHS Compliant

Summary of content (8 pages)

PAGE 1
FQD12P10TM_F085 tm 100V P-Channel MOSFET General Description Features These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode.
PAGE 2
Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units -100 -- -- V -- -0.
PAGE 3
VGS -15.0 V -10.0 V -8.0 V -7.0 V -6.5 V -5.5 V -5.0 V Bottom : -4.5 V Top : -I D, Drain Current [A] 0 10 1 10 -I D , Drain Current [A] 1 10 -1 10 150! 0 25! 10 -55! " Notes : 1. VDS = -40V 2. 250# s Pulse Test " Notes : 1. 250# s Pulse Test 2. TC = 25! -2 10 -1 -1 0 10 10 1 10 2 10 4 6 8 10 -VGS , Gate-Source Voltage [V] -VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.8 1 0.
PAGE 4
(Continued) 3.0 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance -BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 " Notes : 1. VGS = 0 V 2. ID = -250 # A 0.9 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 " Notes : 1. VGS = -10 V 2. ID = -4.7 A 0.5 0.0 -100 200 -50 0 o 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
FQD12P10TM_F085 P-Channel MOSFET Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50K% Qg 200nF 12V -10V 300nF VDS VGS Qgs Qgd DUT -3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL t on td(on) VDD VGS VGS RG t off tr td(off) tf 10% DUT -10V VDS 90% Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS tp ID RG VDD DUT -10V VDS (t) ID (t) IAS BVDSS tp FQD12P10TM_F085 Rev.
PAGE 6
+ VDS DUT _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Compliment of DUT (N-Channel) VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period FQD12P10TM_F085 P-Channel MOSFET Peak Diode Recovery dv/dt Test Circuit & Waveforms 10V Body Diode Reverse Current IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop VDD Body Diode Recovery dv/dt FQD12P10TM_F085 Rev. A 6 www.
PAGE 7
D-PAK MIN0.55 0.91 ±0.10 9.50 ±0.30 0.50 ±0.10 0.76 ±0.10 0.50 ±0.10 1.02 ±0.20 2.30TYP [2.30±0.20] (1.00) (3.05) (2XR0.25) (0.10) 2.70 ±0.20 6.10 ±0.20 9.50 ±0.30 6.60 ±0.20 (5.34) (5.04) (1.50) (0.90) 2.30 ±0.20 (0.70) 2.30TYP [2.30±0.20] (0.50) 2.30 ±0.10 0.89 ±0.10 MAX0.96 (4.34) 2.70 ±0.20 0.80 ±0.20 0.60 ±0.20 (0.50) 6.10 ±0.20 5.34 ±0.30 0.70 ±0.20 6.60 ±0.20 FQD12P10TM_F085 P-Channel MOSFET Package Dimensions 0.76 ±0.
PAGE 8
tm tm FQD12P10TM_F085 P-Channel MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.