Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQD19N10LTM, MOSFET

November 2013

FQD19N10L

N-Channel QFET

MOSFET

100 V, 15.6 A, 100 mΩ

Description

FQD19N10L — N-Channel QFET

MOSFET

FQD19N10L Rev. C1

www.fairchildsemi.com

This N-Channel enhancement mode power MOSFET is

produced using Fairchild Semiconductor’s proprietary

planar stripe and DMOS technology. This advanced

MOSFET technology has been especially tailored to

reduce on-state resistance, and to provide superior

switching performance and high avalanche energy

strength. These devices are suitable for switched mode

power supplies, audio amplifier, DC motor control, and

variable switching power applications.

Features

Absolute Maximum Ratings T

= 25

C unless otherwise noted.

Thermal Characteristics

Symbol Parameter

FQD19N10LTM

Unit

JC

Thermal Resistance, Junction to Case, Max.

2.5

C/W

JA

Thermal Resistance, J

unction to Ambi

ent (

inimum

of 2

oz C

opper),

Max.

110

Thermal Resistance, Junction to Ambient (*1 in

Pad of 2-oz Copper), Max.

D-PAK

• 15.6 A, 100 V, R

DS(on)

= 100 mΩ (Max.) @ V

= 10 V

• Low Gate Charge (Typ. 14 nC)

• Low Crss (Typ. 35 pF)

• 100% Avalanche Tested

Symbol Parameter

FQD19N10LTM

Unit

DSS

Drain-Source Voltage 100 V

Drain Current

- Continuous (T

= 25°C)

15.6 A

- Continuous (T

= 100°C)

9.8 A

Drain Current - Pulsed

(Note 1)

62.4 A

GSS

Gate-Source Voltage ± 20 V

Single Pulsed Avalanche Energy

(Note 2)

220 mJ

Avalanche Current

(Note 1)

15.6 A

Repetitive Avalanche Energy

(Note 1)

5.0 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

6.0 V/ns

Power Dissipation (T

= 25°C) *

2.5 W

Power Dissipation (T

= 25°C)

50 W

- Derate Above 25°C

0.4 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum Lead Temperature for Soldering,

1/8" from Case for 5 Seconds

300 °C

Summary of content (8 pages)

PAGE 1
FQD19N10L N-Channel QFET® MOSFET 100 V, 15.6 A, 100 mΩ Description Features This N-Channel enhancement mode power MOSFET is produced using Fairchild Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength.
PAGE 2
Part Number FQD19N10LTM Electrical Characteristics T Symbol Package D-PAK Top Mark FQD19N10L Packing Method Tape and Reel Reel Size 330 mm Tape Width 16 mm Quantity 2500 units o C = 25 C unless otherwise noted. Parameter Test Conditions Min. Typ. Max. Unit 100 -- -- V -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 μA ΔBVDSS / ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, Referenced to 25°C -- 0.
PAGE 3
VGS 10.0 V 8.0 V 6.0 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V 1 10 ID , Drain Current [A] ID, Drain Current [A] Top : 1 10 150℃ 25℃ 0 10 -55℃ ※ Notes : 1. VDS = 30V 2. 250μ s Pulse Test ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ 0 10 -1 -1 0 10 10 1 10 10 0 2 4 6 8 10 VGS , Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.
PAGE 4
3.0 RDS(ON), (Normalized) Drain-Source On-Resistance BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μA 0.9 0.8 -100 -50 0 50 100 150 2.5 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 7.8 A 0.5 0.0 -100 200 -50 0 o 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
FQD19N10L — N-Channel QFET® MOSFET 50KΩ 200nF 12V VGS Same Type as DUT Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on t off tf Figure 13. Resistive Switching Test Circuit & Waveforms VDS BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L BVDSS IAS ID RG V 10V GS GS VDD ID (t) VDS (t) VDD DUT tp Time tp Figure 14.
PAGE 6
+ VDS _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms ©2000 Fairchild Semiconductor Corporation FQD19N10L Rev. C1 6 www.
PAGE 7
FQD19N10L — N-Channel QFET® MOSFET Mechanical Dimensions Figure 16. TO252 (D-PAK), Molded, 3-Lead, Option AA&AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.