Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQD4P25TM_WS, MOSFET

December 2000

Rev. A2, December 2000

FQD4P25 / FQU4P25

QFET

QFETQFET

QFET

FQD4P25 / FQU4P25

250V P-Channel MOSFET

General Description

These P-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology is especially tailored to minimize

on-state resistance, provide superior switching

performance, and withstand a high energy pulse in the

avalanche and commutation modes. These devices are

well suited for high efficiency switching DC/DC converters.

Features

• -3.1A, -250V, R

DS(on)

= 2.1Ω @V

= -10 V

• Low gate charge ( typical 10 nC)

• Low Crss ( typical 10.3 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

Absolute Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Symbol Parameter FQD4P25 / FQU4P25 Units

DSS

Drain-Source Voltage -250 V

Drain Current

- Continuous (T

= 25°C)

-3.1 A

- Continuous (T

= 100°C)

-1.96 A

Drain Current - Pulsed

(Note 1)

-12.4 A

GSS

Gate-Source Voltage ± 30 V

Single Pulsed Avalanche Energy

(Note 2)

280 mJ

Avalanche Current

(Note 1)

-3.1 A

Repetitive Avalanche Energy

(Note 1)

4.5 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

-5.5 V/ns

Power Dissipation (T

= 25°C) *

2.5 W

Power Dissipation (T

= 25°C)

45 W

- Derate above 25°C 0.36 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering purposes,

1/8” from case for 5 seconds

300 °C

Symbol Parameter Typ Max Units

θJC

Thermal Resistance, Junction-to-Case -- 2.78 °C/W

θJA

Thermal Resistance, Junction-to-Ambient * -- 50 °C/W

θJA

Thermal Resistance, Junction-to-Ambient -- 110 °C/W

* When mounted on the minimum pad size recommended (PCB Mount)

I-PAK

FQU Series

D-PAK

FQD Series

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Summary of content (9 pages)

PAGE 1
QFET TM FQD4P25 / FQU4P25 250V P-Channel MOSFET General Description Features These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand a high energy pulse in the avalanche and commutation modes. These devices are well suited for high efficiency switching DC/DC converters. • • • • • • -3.
PAGE 2
Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units -250 -- -- V -- -0.
PAGE 3
FQD4P25 / FQU4P25 Typical Characteristics 1 10 VGS -15.0 V -10.0 V -8.0 V -7.0 V -6.5 V -6.0 V Bottom : -5.5 V 1 10 0 10 -I D , Drain Current [A] -I D, Drain Current [A] Top : -1 10 ※ Notes : 1. 250μs Pulse Test 2. TC = 25℃ 0 10 150℃ 25℃ ※ Notes : 1. VDS = -50V 2. 250μs Pulse Test -55℃ -2 -1 10 -1 0 10 10 1 10 2 10 4 6 8 10 -VGS , Gate-Source Voltage [V] -VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2.
PAGE 4
FQD4P25 / FQU4P25 Typical Characteristics (Continued) 3.0 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance -BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 0.9 ※ Note : 1. VGS = 0 V 2. ID = -250 μA 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 ※ Notes : 1. VGS = -10 V 2. ID = -2.0 A 0.5 0.0 -100 200 -50 o 0 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8.
PAGE 5
FQD4P25 / FQU4P25 Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V -10V 300nF VDS VGS Qgs Qgd DUT -3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL t on VDD VGS RG td(on) VGS t off tr td(off) tf 10% DUT -10V VDS 90% Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS tp ID RG VDD DUT -10V tp ©2000 Fairchild Semiconductor International VDD Time VDS (t) ID (t) I
PAGE 6
FQD4P25 / FQU4P25 Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Compliment of DUT (N-Channel) VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop VDD Body Diode Recovery dv/dt ©2000 Fairchild Semiconductor International Rev.
PAGE 7
DPAK MIN0.55 0.91 ±0.10 9.50 ±0.30 0.50 ±0.10 0.76 ±0.10 0.50 ±0.10 1.02 ±0.20 2.30TYP [2.30±0.20] (1.00) (3.05) (2XR0.25) (0.10) 2.70 ±0.20 6.10 ±0.20 9.50 ±0.30 6.60 ±0.20 (5.34) (5.04) (1.50) (0.90) 2.30 ±0.20 (0.70) 2.30TYP [2.30±0.20] (0.50) 2.30 ±0.10 0.89 ±0.10 MAX0.96 (4.34) 2.70 ±0.20 0.80 ±0.20 0.60 ±0.20 (0.50) 6.10 ±0.20 5.34 ±0.30 0.70 ±0.20 6.60 ±0.20 0.76 ±0.10 ©2000 Fairchild Semiconductor International Rev.
PAGE 8
(Continued) IPAK 2.30 ±0.20 6.60 ±0.20 5.34 ±0.20 0.76 ±0.10 2.30TYP [2.30±0.20] ©2000 Fairchild Semiconductor International 0.50 ±0.10 16.10 ±0.30 6.10 ±0.20 0.70 ±0.20 (0.50) 9.30 ±0.30 MAX0.96 (4.34) 1.80 ±0.20 0.80 ±0.10 0.60 ±0.20 (0.50) 2.30TYP [2.30±0.20] 0.50 ±0.10 Rev.
PAGE 9
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