Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQD6N50CTM, MOSFET

November 2013

FQD6N50C — N-Channel QFET

MOSFET

FQD6N50C Rev. C1

www.fairchildsemi.com

Absolute Maximum Ratings T

= 25°C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FQD6N50CTM Unit

DSS

Drain-Source Voltage 500 V

Drain Current

- Continuous (T

= 25°C)

4.5 A

- Continuous (T

= 100°C)

2.7 A

Drain Current - Pulsed

(Note 1)

18 A

GSS

Gate-Source Voltage ± 30 V

Single Pulsed Avalanche Energy

(Note 2)

300 mJ

Avalanche Current

(Note 1)

4.5 A

Repetitive Avalanche Energy

(Note 1)

6.1 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

4.5 V/ns

Power Dissipation (T

= 25°C)*

2.5 W

Power Dissipation (T

= 25°C)

61 W

- Derate above 25°C 0.49 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds

300 °C

Symbol Parameter FQD6N50CTM Unit

θJC

Thermal Resistance, Junction-to-Case, Max. 2.05

°C/W

θJA

Thermal Resistance, Junction-to-Ambient (minimum pad of 2 oz copper), Max. 110

Thermal Resistance, Junction-to-Ambient (* 1 in

pad of 2 oz copper), Max.

FQD6N50C

N-Channel QFET

MOSFET

500 V, 4.5 A, 1.2 Ω

Features

• 4.5 A, 500 V, R

DS(on)

= 1.2 Ω (Max.) @V

= 10 V, I

= 2.25 A

• Low Gate Charge (Typ. 19 nC)

• Low Crss (Typ.15 pF)

• 100% avalanche tested

Description

This N-Channel enhancement mode power MOSFET is

produced using Fairchild Semiconductor’s proprietary

planar stripe and DMOS technology. This advanced

MOSFET technology has been especially tailored to reduce

on-state resistance, and to provide superior switching

performance and high avalanche energy strength. These

devices are suitable for switched mode power supplies,

active power factor correction (PFC), and electronic lamp

ballasts.

D-PAK

Summary of content (8 pages)

PAGE 1
FQD6N50C N-Channel QFET® MOSFET 500 V, 4.5 A, 1.2 Ω Features Description • 4.5 A, 500 V, RDS(on) = 1.2 Ω (Max.) @VGS = 10 V, ID = 2.25 A This N-Channel enhancement mode power MOSFET is produced using Fairchild Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength.
PAGE 2
Device Marking FQD6N50C Device FQD6N50CTM Electrical Characteristics Symbol Package D-PAK Reel Size 330 mm Tape Width 16 mm Quantity 2500 units TC = 25°C unless otherwise noted. Parameter Test Conditions Min Typ Max Unit 500 -- -- V -- 0.
PAGE 3
FQD6N50C — N-Channel QFET® MOSFET Typical Characteristics VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V Bottom : 5.0 V Top : ID, Drain Current [A] 1 10 ID, Drain Current [A] 1 10 0 10 -1 10 o 150 C o 25 C o 0 10 -55 C ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ ※ Notes : 1. VDS = 40V 2. 250μ s Pulse Test -1 -1 0 10 10 1 10 10 2 4 6 8 10 VGS, Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 1 3.
PAGE 4
(Continued) 3.0 RDS(ON), (Normalized) Drain-Source On-Resistance BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μA 0.9 0.8 -100 -50 0 50 100 150 2.5 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 2.25 A 0.5 0.0 -100 200 -50 0 o TJ, Junction Temperature [ C] 50 100 150 200 o TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs Temperature Figure 8.
PAGE 5
FQD6N50C — N-Channel QFET® MOSFET Figure 12. Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ 200nF 12V Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 13. Resistive Switching Test Circuit & Waveforms VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on tf t off Figure 14.
PAGE 6
FQD6N50C — N-Channel QFET® MOSFET Figure 15.
PAGE 7
FQD6N50C — N-Channel QFET® MOSFET Mechanical Dimensions TO-252 3L (DPAK) Figure 16. TO252 (D-PAK), Molded, 3 Lead, Option AA&AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.